Module: Mesa Branch: main Commit: 6c44d92362ba46ee56ec4ec91f75a3c2f8286d79 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c44d92362ba46ee56ec4ec91f75a3c2f8286d79
Author: Qiang Yu <[email protected]> Date: Tue Nov 1 15:52:53 2022 +0800 ac/llvm,radeonsi: lower attribute ring intrinsics in nir Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010> --- src/amd/llvm/ac_nir_to_llvm.c | 6 ----- src/gallium/drivers/radeonsi/si_nir_lower_abi.c | 36 +++++++++++++++++++++++++ src/gallium/drivers/radeonsi/si_shader_llvm.c | 36 ------------------------- 3 files changed, 36 insertions(+), 42 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 3f8aec622ca..796fb2e2c78 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3628,12 +3628,6 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_merged_wave_info_amd: result = ac_get_arg(&ctx->ac, ctx->args->merged_wave_info); break; - case nir_intrinsic_load_ring_attr_offset_amd: { - LLVMValueRef offset = ac_get_arg(&ctx->ac, ctx->args->gs_attr_offset); - offset = ac_unpack_param(&ctx->ac, offset, 0, 15); - result = LLVMBuildShl(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, 9, false), ""); - break; - } case nir_intrinsic_load_ordered_id_amd: result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info), 0, 12); break; diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c index 4576317879f..3f0f0080b6f 100644 --- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c +++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c @@ -79,6 +79,34 @@ static nir_ssa_def *get_num_vert_per_prim(nir_builder *b, struct si_shader *shad return nir_imm_int(b, num_vertices); } +static nir_ssa_def *build_attr_ring_desc(nir_builder *b, struct si_shader *shader, + struct si_shader_args *args) +{ + struct si_shader_selector *sel = shader->selector; + + nir_ssa_def *attr_address = + sel->stage == MESA_SHADER_VERTEX && sel->info.base.vs.blit_sgprs_amd ? + load_internal_binding(b, args, SI_GS_ATTRIBUTE_RING) : + ac_nir_load_arg(b, &args->ac, args->gs_attr_address); + + unsigned stride = 16 * shader->info.nr_param_exports; + nir_ssa_def *comp[] = { + attr_address, + nir_imm_int(b, S_008F04_BASE_ADDRESS_HI(sel->screen->info.address32_hi) | + S_008F04_STRIDE(stride) | + S_008F04_SWIZZLE_ENABLE_GFX11(3) /* 16B */), + nir_imm_int(b, 0xffffffff), + nir_imm_int(b, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | + S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | + S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | + S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | + S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_32_32_32_FLOAT) | + S_008F0C_INDEX_STRIDE(2) /* 32 elements */), + }; + + return nir_vec(b, comp, 4); +} + static bool lower_abi_instr(nir_builder *b, nir_instr *instr, struct lower_abi_state *s) { if (instr->type != nir_instr_type_intrinsic) @@ -253,6 +281,14 @@ static bool lower_abi_instr(nir_builder *b, nir_instr *instr, struct lower_abi_s nir_buffer_atomic_add_amd(b, 32, buf, prim_count, .base = offset); break; } + case nir_intrinsic_load_ring_attr_amd: + replacement = build_attr_ring_desc(b, shader, args); + break; + case nir_intrinsic_load_ring_attr_offset_amd: { + nir_ssa_def *offset = ac_nir_unpack_arg(b, &args->ac, args->ac.gs_attr_offset, 0, 15); + replacement = nir_ishl_imm(b, offset, 9); + break; + } default: return false; } diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index fc9ea32c161..f669040da12 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -700,39 +700,6 @@ void si_build_wrapper_function(struct si_shader_context *ctx, struct ac_llvm_poi LLVMBuildRet(builder, ret); } -static LLVMValueRef si_llvm_build_attr_ring_desc(struct si_shader_context *ctx) -{ - struct si_shader *shader = ctx->shader; - - LLVMValueRef attr_address; - if (ctx->stage == MESA_SHADER_VERTEX && shader->selector->info.base.vs.blit_sgprs_amd) { - struct ac_llvm_pointer ring_ptr = - ac_get_ptr_arg(&ctx->ac, &ctx->args->ac, ctx->args->internal_bindings); - ring_ptr.pointee_type = ctx->ac.i32; - attr_address = ac_build_load_to_sgpr(&ctx->ac, ring_ptr, - LLVMConstInt(ctx->ac.i32, SI_GS_ATTRIBUTE_RING * 4, 0)); - } else { - attr_address = ac_get_arg(&ctx->ac, ctx->args->gs_attr_address); - } - - unsigned stride = 16 * shader->info.nr_param_exports; - LLVMValueRef attr_desc[4] = { - attr_address, - LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi) | - S_008F04_STRIDE(stride) | - S_008F04_SWIZZLE_ENABLE_GFX11(3) /* 16B */, 0), - LLVMConstInt(ctx->ac.i32, 0xffffffff, 0), - LLVMConstInt(ctx->ac.i32, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | - S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | - S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | - S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | - S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_32_32_32_FLOAT) | - S_008F0C_INDEX_STRIDE(2) /* 32 elements */, 0), - }; - - return ac_build_gather_values(&ctx->ac, attr_desc, 4); -} - static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrinsic_op op) { struct si_shader_context *ctx = si_shader_context_from_abi(abi); @@ -747,9 +714,6 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin case nir_intrinsic_load_ring_esgs_amd: return ctx->esgs_ring; - case nir_intrinsic_load_ring_attr_amd: - return si_llvm_build_attr_ring_desc(ctx); - case nir_intrinsic_load_lds_ngg_scratch_base_amd: return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_scratch.value, ctx->ac.i32, "");
