Module: Mesa Branch: main Commit: 2d150f3ecd7fdb564bb837924951f8f8e5c4d3aa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d150f3ecd7fdb564bb837924951f8f8e5c4d3aa
Author: Jason Ekstrand <[email protected]> Date: Sat Sep 3 00:13:23 2022 -0500 hasvk: Drop more DG2 code v2: remove unused devinfo (Lionel) Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852> --- src/intel/vulkan_hasvk/anv_allocator.c | 12 +----------- src/intel/vulkan_hasvk/anv_batch_chain.c | 12 ++---------- src/intel/vulkan_hasvk/anv_blorp.c | 18 ------------------ src/intel/vulkan_hasvk/anv_cmd_buffer.c | 14 ++++---------- src/intel/vulkan_hasvk/anv_device.c | 10 +--------- src/intel/vulkan_hasvk/anv_nir_compute_push_layout.c | 3 +-- src/intel/vulkan_hasvk/anv_perf.c | 3 +-- 7 files changed, 10 insertions(+), 62 deletions(-) diff --git a/src/intel/vulkan_hasvk/anv_allocator.c b/src/intel/vulkan_hasvk/anv_allocator.c index b223a354bdd..95af95a245e 100644 --- a/src/intel/vulkan_hasvk/anv_allocator.c +++ b/src/intel/vulkan_hasvk/anv_allocator.c @@ -373,12 +373,6 @@ anv_block_pool_init(struct anv_block_pool *pool, { VkResult result; - if (device->info->verx10 >= 125) { - /* Make sure VMA addresses are 2MiB aligned for the block pool */ - assert(anv_is_aligned(start_address, 2 * 1024 * 1024)); - assert(anv_is_aligned(initial_size, 2 * 1024 * 1024)); - } - pool->name = name; pool->device = device; pool->use_relocations = anv_use_relocations(device->physical); @@ -843,8 +837,6 @@ anv_state_pool_init(struct anv_state_pool *pool, assert(start_offset < INT32_MAX - (int32_t)BLOCK_POOL_MEMFD_SIZE); uint32_t initial_size = block_size * 16; - if (device->info->verx10 >= 125) - initial_size = MAX2(initial_size, 2 * 1024 * 1024); VkResult result = anv_block_pool_init(&pool->block_pool, device, name, base_address + start_offset, @@ -1472,10 +1464,8 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool, * * so nothing will ever touch the top page. */ - const enum anv_bo_alloc_flags alloc_flags = - devinfo->verx10 < 125 ? ANV_BO_ALLOC_32BIT_ADDRESS : 0; VkResult result = anv_device_alloc_bo(device, "scratch", size, - alloc_flags, + ANV_BO_ALLOC_32BIT_ADDRESS, 0 /* explicit_address */, &bo); if (result != VK_SUCCESS) diff --git a/src/intel/vulkan_hasvk/anv_batch_chain.c b/src/intel/vulkan_hasvk/anv_batch_chain.c index 994725fd056..08432b7eee5 100644 --- a/src/intel/vulkan_hasvk/anv_batch_chain.c +++ b/src/intel/vulkan_hasvk/anv_batch_chain.c @@ -792,16 +792,8 @@ anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer, cmd_buffer->bt_next.map += bt_size; cmd_buffer->bt_next.alloc_size -= bt_size; - if (cmd_buffer->device->info->verx10 >= 125) { - /* We're using 3DSTATE_BINDING_TABLE_POOL_ALLOC to change the binding - * table address independently from surface state base address. We no - * longer need any sort of offsetting. - */ - *state_offset = 0; - } else { - assert(bt_block->offset < 0); - *state_offset = -bt_block->offset; - } + assert(bt_block->offset < 0); + *state_offset = -bt_block->offset; return state; } diff --git a/src/intel/vulkan_hasvk/anv_blorp.c b/src/intel/vulkan_hasvk/anv_blorp.c index 209e33222a3..52bcb4c60a1 100644 --- a/src/intel/vulkan_hasvk/anv_blorp.c +++ b/src/intel/vulkan_hasvk/anv_blorp.c @@ -1787,7 +1787,6 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, /* Multisampling with multi-planar formats is not supported */ assert(image->n_planes == 1); - const struct intel_device_info *devinfo = cmd_buffer->device->info; struct blorp_batch batch; anv_blorp_batch_init(cmd_buffer, &batch, BLORP_BATCH_PREDICATE_ENABLE * predicate + @@ -1824,11 +1823,6 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_TILE_CACHE_FLUSH_BIT | - (devinfo->verx10 == 120 ? - ANV_PIPE_DEPTH_STALL_BIT : 0) | - (devinfo->verx10 == 125 ? - ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | - ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0) | ANV_PIPE_PSS_STALL_SYNC_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT, "before fast clear mcs"); @@ -1851,9 +1845,6 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - (devinfo->verx10 == 120 ? - ANV_PIPE_TILE_CACHE_FLUSH_BIT | - ANV_PIPE_DEPTH_STALL_BIT : 0) | ANV_PIPE_PSS_STALL_SYNC_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT, "after fast clear mcs"); @@ -1879,7 +1870,6 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, anv_image_aux_layers(image, aspect, level)); const uint32_t plane = anv_image_aspect_to_plane(image, aspect); - const struct intel_device_info *devinfo = cmd_buffer->device->info; struct blorp_batch batch; anv_blorp_batch_init(cmd_buffer, &batch, @@ -1921,11 +1911,6 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_TILE_CACHE_FLUSH_BIT | - (devinfo->verx10 == 120 ? - ANV_PIPE_DEPTH_STALL_BIT : 0) | - (devinfo->verx10 == 125 ? - ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | - ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0) | ANV_PIPE_PSS_STALL_SYNC_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT, "before fast clear ccs"); @@ -1953,9 +1938,6 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - (devinfo->verx10 == 120 ? - ANV_PIPE_TILE_CACHE_FLUSH_BIT | - ANV_PIPE_DEPTH_STALL_BIT : 0) | ANV_PIPE_PSS_STALL_SYNC_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT, "after fast clear ccs"); diff --git a/src/intel/vulkan_hasvk/anv_cmd_buffer.c b/src/intel/vulkan_hasvk/anv_cmd_buffer.c index 25e15265bba..6ab7f4d3d7c 100644 --- a/src/intel/vulkan_hasvk/anv_cmd_buffer.c +++ b/src/intel/vulkan_hasvk/anv_cmd_buffer.c @@ -591,16 +591,10 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer) cmd_buffer->device->info->ver < 8 ? 32 : 64; const unsigned aligned_total_push_constants_size = ALIGN(total_push_constants_size, push_constant_alignment); - struct anv_state state; - if (devinfo->verx10 >= 125) { - state = anv_state_stream_alloc(&cmd_buffer->general_state_stream, - aligned_total_push_constants_size, - push_constant_alignment); - } else { - state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, - aligned_total_push_constants_size, - push_constant_alignment); - } + struct anv_state state = + anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, + aligned_total_push_constants_size, + push_constant_alignment); void *dst = state.map; const void *src = (char *)data + (range->start * 32); diff --git a/src/intel/vulkan_hasvk/anv_device.c b/src/intel/vulkan_hasvk/anv_device.c index 76dbd0945a4..b1a36273717 100644 --- a/src/intel/vulkan_hasvk/anv_device.c +++ b/src/intel/vulkan_hasvk/anv_device.c @@ -2909,15 +2909,7 @@ VkResult anv_CreateDevice( if (result != VK_SUCCESS) goto fail_instruction_state_pool; - if (device->info->verx10 >= 125) { - /* We're using 3DSTATE_BINDING_TABLE_POOL_ALLOC to give the binding - * table its own base address separately from surface state base. - */ - result = anv_state_pool_init(&device->binding_table_pool, device, - "binding table pool", - BINDING_TABLE_POOL_MIN_ADDRESS, 0, - BINDING_TABLE_POOL_BLOCK_SIZE); - } else if (!anv_use_relocations(physical_device)) { + if (!anv_use_relocations(physical_device)) { int64_t bt_pool_offset = (int64_t)BINDING_TABLE_POOL_MIN_ADDRESS - (int64_t)SURFACE_STATE_POOL_MIN_ADDRESS; assert(INT32_MIN < bt_pool_offset && bt_pool_offset < 0); diff --git a/src/intel/vulkan_hasvk/anv_nir_compute_push_layout.c b/src/intel/vulkan_hasvk/anv_nir_compute_push_layout.c index bf173fe56d9..863ac21c04b 100644 --- a/src/intel/vulkan_hasvk/anv_nir_compute_push_layout.c +++ b/src/intel/vulkan_hasvk/anv_nir_compute_push_layout.c @@ -37,7 +37,6 @@ anv_nir_compute_push_layout(nir_shader *nir, void *mem_ctx) { const struct brw_compiler *compiler = pdevice->compiler; - const struct intel_device_info *devinfo = compiler->devinfo; memset(map->push_ranges, 0, sizeof(map->push_ranges)); bool has_const_ubo = false; @@ -95,7 +94,7 @@ anv_nir_compute_push_layout(nir_shader *nir, push_end = MAX2(push_end, push_reg_mask_end); } - if (nir->info.stage == MESA_SHADER_COMPUTE && devinfo->verx10 < 125) { + if (nir->info.stage == MESA_SHADER_COMPUTE) { /* For compute shaders, we always have to have the subgroup ID. The * back-end compiler will "helpfully" add it for us in the last push * constant slot. Yes, there is an off-by-one error here but that's diff --git a/src/intel/vulkan_hasvk/anv_perf.c b/src/intel/vulkan_hasvk/anv_perf.c index b0372ec35ae..d252fa7278e 100644 --- a/src/intel/vulkan_hasvk/anv_perf.c +++ b/src/intel/vulkan_hasvk/anv_perf.c @@ -138,8 +138,7 @@ anv_device_perf_open(struct anv_device *device, uint64_t metric_id) * Temporary disable this option on Gfx12.5+, kernel doesn't appear to * support it. */ - if (intel_perf_has_global_sseu(device->physical->perf) && - device->info->verx10 < 125) { + if (intel_perf_has_global_sseu(device->physical->perf)) { properties[p++] = DRM_I915_PERF_PROP_GLOBAL_SSEU; properties[p++] = (uintptr_t) &device->physical->perf->sseu; }
