Module: Mesa Branch: staging/23.0 Commit: 1c6b8b8ad69f162ac8c32a2e3ea5afc70f852d1f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c6b8b8ad69f162ac8c32a2e3ea5afc70f852d1f
Author: Gert Wollny <[email protected]> Date: Tue Jan 17 09:03:26 2023 +0100 r600/sfn: Fix readport check We have to take multi-slot instructions into account, and we don't fail when there are still possible bank swizzle values to be checked. For clarity also rename the bank swizzle iterator iterator. Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6 r600/sfn: rewrite NIR backend Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739> (cherry picked from commit ca5bbff558d1de7af3410e659dc0ac6c042cdee3) --- .pick_status.json | 2 +- src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp | 22 ++++++++++++---------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 06c0b494dca..8113bf47a7d 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -733,7 +733,7 @@ "description": "r600/sfn: Fix readport check", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "79ca456b4837b3bc21cf9ef3c03c505c4b4909f6" }, diff --git a/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp b/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp index 9e6197da863..2da0ec1aa6d 100644 --- a/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp @@ -587,22 +587,24 @@ AluInstr::check_readport_validation(PRegister old_src, PVirtualValue new_src) co assert(nsrc * m_alu_slots == m_src.size()); for (int s = 0; s < m_alu_slots && success; ++s) { - for (AluBankSwizzle i = alu_vec_012; i != alu_vec_unknown; ++i) { - auto ireg = m_src.begin() + s * nsrc; - - AluReadportReservation rpr = rpr_sum; - PVirtualValue s[3]; + PVirtualValue src[3]; + auto ireg = m_src.begin() + s * nsrc; - for (unsigned i = 0; i < nsrc; ++i, ++ireg) - s[i] = old_src->equal_to(**ireg) ? new_src : *ireg; + for (unsigned i = 0; i < nsrc; ++i, ++ireg) + src[i] = old_src->equal_to(**ireg) ? new_src : *ireg; - if (rpr.schedule_vec_src(s, nsrc, i)) { + AluBankSwizzle bs = alu_vec_012; + while (bs != alu_vec_unknown) { + AluReadportReservation rpr = rpr_sum; + if (rpr.schedule_vec_src(src, nsrc, bs)) { rpr_sum = rpr; break; - } else { - success = false; } + ++bs; } + + if (bs == alu_vec_unknown) + success = false; } return success; }
