Module: Mesa Branch: main Commit: 780f3e2e6b6ce2ffd1bb8b6daeeb40244727edd5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=780f3e2e6b6ce2ffd1bb8b6daeeb40244727edd5
Author: Kenneth Graunke <[email protected]> Date: Mon Jan 9 16:44:26 2023 -0800 intel/compiler: Delete all the A64 atomic variants for type sizes These are handled identically in almost all cases. There is one place in the legacy surface lowering that was obtaining the bitsize from the opcode, but the LSC-based lowering uses (type_sz(inst->dst.type) * 8) for that and works just fine. If we just do that in the legacy lowering too, then we don't need this plethora of opcodes. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rohan Garg <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20604> --- src/intel/compiler/brw_eu_defines.h | 5 -- src/intel/compiler/brw_fs.cpp | 10 ---- src/intel/compiler/brw_fs.h | 2 - src/intel/compiler/brw_fs_nir.cpp | 63 ++------------------------ src/intel/compiler/brw_lower_logical_sends.cpp | 53 ++++++---------------- src/intel/compiler/brw_shader.cpp | 15 ------ 6 files changed, 16 insertions(+), 132 deletions(-) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 15add869ce7..537203556c9 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -412,11 +412,6 @@ enum opcode { SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL, SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, - SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL, - SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL, - SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL, - SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL, - SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL, SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 844a54303ed..a816ad9d438 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -779,11 +779,6 @@ fs_inst::components_read(unsigned i) const return i == 1 ? src[2].ud : 1; case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: assert(src[2].file == IMM); return i == 1 ? lsc_op_num_data_values(src[2].ud) : 1; @@ -5193,11 +5188,6 @@ get_lowered_simd_width(const struct brw_compiler *compiler, return inst->exec_size; case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: return devinfo->has_lsc ? MIN2(16, inst->exec_size) : 8; case SHADER_OPCODE_URB_READ_LOGICAL: diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index df97f7ebacd..581cafab1fc 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -364,8 +364,6 @@ public: fs_reg surface); void nir_emit_global_atomic(const brw::fs_builder &bld, nir_intrinsic_instr *instr); - void nir_emit_global_atomic_float(const brw::fs_builder &bld, - nir_intrinsic_instr *instr); void nir_emit_texture(const brw::fs_builder &bld, nir_tex_instr *instr); void nir_emit_jump(const brw::fs_builder &bld, diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index a74a570f62d..53f5101b5c5 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4877,13 +4877,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr case nir_intrinsic_global_atomic_xor: case nir_intrinsic_global_atomic_exchange: case nir_intrinsic_global_atomic_comp_swap: - nir_emit_global_atomic(bld, instr); - break; case nir_intrinsic_global_atomic_fadd: case nir_intrinsic_global_atomic_fmin: case nir_intrinsic_global_atomic_fmax: case nir_intrinsic_global_atomic_fcomp_swap: - nir_emit_global_atomic_float(bld, instr); + nir_emit_global_atomic(bld, instr); break; case nir_intrinsic_load_global_const_block_intel: { @@ -6073,70 +6071,15 @@ fs_visitor::nir_emit_global_atomic(const fs_builder &bld, switch (nir_dest_bit_size(instr->dest)) { case 16: { fs_reg dest32 = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL, - retype(dest32, dest.type), - srcs, A64_LOGICAL_NUM_SRCS); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_UW), dest32); - break; - } - case 32: - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, dest, - srcs, A64_LOGICAL_NUM_SRCS); - break; - case 64: - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL, dest, - srcs, A64_LOGICAL_NUM_SRCS); - break; - default: - unreachable("Unsupported bit size"); - } -} - -void -fs_visitor::nir_emit_global_atomic_float(const fs_builder &bld, - nir_intrinsic_instr *instr) -{ - int op = lsc_aop_for_nir_intrinsic(instr); - - assert(nir_intrinsic_infos[instr->intrinsic].has_dest); - fs_reg dest = get_nir_dest(instr->dest); - - fs_reg addr = get_nir_src(instr->src[0]); - - assert(op != LSC_OP_ATOMIC_INC && op != LSC_OP_ATOMIC_DEC); - fs_reg data = expand_to_32bit(bld, get_nir_src(instr->src[1])); - - if (op == LSC_OP_ATOMIC_FCMPXCHG) { - fs_reg tmp = bld.vgrf(data.type, 2); - fs_reg sources[2] = { - data, - expand_to_32bit(bld, get_nir_src(instr->src[2])) - }; - bld.LOAD_PAYLOAD(tmp, sources, 2, 0); - data = tmp; - } - - fs_reg srcs[A64_LOGICAL_NUM_SRCS]; - srcs[A64_LOGICAL_ADDRESS] = addr; - srcs[A64_LOGICAL_SRC] = data; - srcs[A64_LOGICAL_ARG] = brw_imm_ud(op); - srcs[A64_LOGICAL_ENABLE_HELPERS] = brw_imm_ud(0); - - switch (nir_dest_bit_size(instr->dest)) { - case 16: { - fs_reg dest32 = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL, + bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, retype(dest32, dest.type), srcs, A64_LOGICAL_NUM_SRCS); bld.MOV(retype(dest, BRW_REGISTER_TYPE_UW), dest32); break; } case 32: - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL, dest, - srcs, A64_LOGICAL_NUM_SRCS); - break; case 64: - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL, dest, + bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, dest, srcs, A64_LOGICAL_NUM_SRCS); break; default: diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 3873806ddd7..a536d1a4f76 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -2035,12 +2035,7 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE_STORE_L1STATE_L3MOCS, false /* has_dest */); break; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: { - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: + case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: { /* Bspec: Atomic instruction -> Cache section: * * Atomic messages are always forced to "un-cacheable" in the L1 @@ -2211,35 +2206,18 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst) break; case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - desc = brw_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, 32, - lsc_op_to_legacy_atomic(arg), - !inst->dst.is_null()); - break; - - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL: - desc = brw_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, 16, - lsc_op_to_legacy_atomic(arg), - !inst->dst.is_null()); - break; - - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: - desc = brw_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, 64, - lsc_op_to_legacy_atomic(arg), - !inst->dst.is_null()); - break; - - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: - desc = brw_dp_a64_untyped_atomic_float_desc(devinfo, inst->exec_size, - 16, /* bit_size */ - lsc_op_to_legacy_atomic(arg), - !inst->dst.is_null()); - break; - - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: - desc = brw_dp_a64_untyped_atomic_float_desc(devinfo, inst->exec_size, - 32, /* bit_size */ - lsc_op_to_legacy_atomic(arg), - !inst->dst.is_null()); + if (lsc_opcode_is_atomic_float((enum lsc_opcode) arg)) { + desc = + brw_dp_a64_untyped_atomic_float_desc(devinfo, inst->exec_size, + type_sz(inst->dst.type) * 8, + lsc_op_to_legacy_atomic(arg), + !inst->dst.is_null()); + } else { + desc = brw_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, + type_sz(inst->dst.type) * 8, + lsc_op_to_legacy_atomic(arg), + !inst->dst.is_null()); + } break; default: @@ -2729,11 +2707,6 @@ fs_visitor::lower_logical_sends() case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 4412b366ae5..d4839cb22c5 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -321,16 +321,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) return "a64_byte_scattered_write_logical"; case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: return "a64_untyped_atomic_logical"; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL: - return "a64_untyped_atomic_int16_logical"; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: - return "a64_untyped_atomic_int64_logical"; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: - return "a64_untyped_atomic_float16_logical"; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: - return "a64_untyped_atomic_float32_logical"; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: - return "a64_untyped_atomic_float64_logical"; case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: return "typed_atomic_logical"; case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: @@ -1112,11 +1102,6 @@ backend_instruction::has_side_effects() const case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
