Module: Mesa Branch: main Commit: 1617dac6c3a4212d0e254c05f9f42f0bf2f5d52b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1617dac6c3a4212d0e254c05f9f42f0bf2f5d52b
Author: Tatsuyuki Ishi <[email protected]> Date: Sat Jan 14 18:30:32 2023 +0900 radv: Fix depth-only-with-discard when epilogs are used. For a depth-only-with-discard pipeline, spi_shader_col_format needs to be fixed up to a single channel export, or otherwise discard will not work. Since col_format can change depending on the dynamic state, precompute the need for this workaround on pipeline creation and apply it when emitting prolog states. Fixes: eb07a11b8f4 ("radv: add support for compiling PS epilogs on-demand") Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20704> --- src/amd/vulkan/radv_cmd_buffer.c | 9 +++++++-- src/amd/vulkan/radv_pipeline.c | 12 ++++++------ src/amd/vulkan/radv_private.h | 1 + 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b61dc02277f..a2cc6dab4c3 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1899,8 +1899,10 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader if (cmd_buffer->state.emitted_ps_epilog == ps_epilog && !pipeline_is_dirty) return; - radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, - ps_epilog->spi_shader_col_format); + uint32_t col_format = ps_epilog->spi_shader_col_format; + if (pipeline->need_null_export_workaround && !col_format) + col_format = V_028714_SPI_SHADER_32_R; + radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, col_format); radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, ac_get_cb_shader_mask(ps_epilog->spi_shader_col_format)); @@ -8541,6 +8543,9 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r } cmd_buffer->state.col_format_non_compacted = ps_epilog->spi_shader_col_format; + if (cmd_buffer->state.graphics_pipeline->need_null_export_workaround && + !cmd_buffer->state.col_format_non_compacted) + cmd_buffer->state.col_format_non_compacted = V_028714_SPI_SHADER_32_R; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS; } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 8e1f1a46157..cede994a732 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -5232,12 +5232,12 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv * color and Z formats to SPI_SHADER_ZERO. The hw will skip export * instructions if any are present. */ - if ((device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) && - !blend.spi_shader_col_format) { - if (!ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask) { - blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; - pipeline->col_format_non_compacted = V_028714_SPI_SHADER_32_R; - } + pipeline->need_null_export_workaround = + (device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) && + !ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask; + if (pipeline->need_null_export_workaround && !blend.spi_shader_col_format) { + blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; + pipeline->col_format_non_compacted = V_028714_SPI_SHADER_32_R; } if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 5ab7de9daa9..93b69dd4c45 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2086,6 +2086,7 @@ struct radv_graphics_pipeline { bool mrt0_is_dual_src; uint8_t need_src_alpha; + bool need_null_export_workaround; bool uses_drawid; bool uses_baseinstance;
