Module: Mesa Branch: main Commit: 9c658b1fc86078efe5e71f68519e9216de0f46de URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c658b1fc86078efe5e71f68519e9216de0f46de
Author: Jason Ekstrand <[email protected]> Date: Tue Nov 23 12:48:27 2021 -0600 intel/fs/validate: Assert SEND [extended] descriptors are uniform This is required by code-gen since it generates a 1-wide OR and it'll blow up if the register width > 1. It's also way better than the "your register is the wrong size" assert you get from the more generic validation check. Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094> --- src/intel/compiler/brw_fs_validate.cpp | 12 +++++++++++- src/intel/compiler/brw_lower_logical_sends.cpp | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_validate.cpp b/src/intel/compiler/brw_fs_validate.cpp index 5c9dbf81062..40ba7edcb60 100644 --- a/src/intel/compiler/brw_fs_validate.cpp +++ b/src/intel/compiler/brw_fs_validate.cpp @@ -87,7 +87,8 @@ fs_visitor::validate() { #ifndef NDEBUG foreach_block_and_inst (block, fs_inst, inst, cfg) { - if (inst->opcode == SHADER_OPCODE_URB_WRITE_LOGICAL) { + switch (inst->opcode) { + case SHADER_OPCODE_URB_WRITE_LOGICAL: { const unsigned header_size = 1 + unsigned(inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE) + unsigned(inst->src[URB_LOGICAL_SRC_CHANNEL_MASK].file != BAD_FILE); @@ -99,6 +100,15 @@ fs_visitor::validate() } fsv_assert_eq(header_size + data_size, inst->mlen); + break; + } + + case SHADER_OPCODE_SEND: + fsv_assert(is_uniform(inst->src[0]) && is_uniform(inst->src[1])); + break; + + default: + break; } if (inst->is_3src(compiler)) { diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 1faae680513..dfbb8233190 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -370,6 +370,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); ubld.AND(desc, dynamic_msaa_flags(prog_data), brw_imm_ud(BRW_WM_MSAA_FLAG_COARSE_DISPATCH)); + desc = component(desc, 0); } uint32_t ex_desc = 0;
