Module: Mesa Branch: main Commit: 97aa8d9547ec00109853f1a4a43e4abfad7f6aa7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=97aa8d9547ec00109853f1a4a43e4abfad7f6aa7
Author: Hans-Kristian Arntzen <[email protected]> Date: Sun Feb 12 15:40:31 2023 +0100 radv: Fix invalid 64-bit shift. For sync2 bits, overflow can happen. Use BITFIELD64_BIT to align with ANV. Signed-off-by: Hans-Kristian Arntzen <[email protected]> Fixes: 8df17163c78 ("radv: implement vkCmdWaitEvents2KHR") Reviewed-by: Timur Kristóf <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21271> --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 9a8b8835a42..5a02befa8e5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5303,7 +5303,7 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 src_fla u_foreach_bit64(b, src_flags) { - switch ((VkAccessFlags2)(1 << b)) { + switch ((VkAccessFlags2)BITFIELD64_BIT(b)) { case VK_ACCESS_2_SHADER_WRITE_BIT: case VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT: /* since the STORAGE bit isn't set we know that this is a meta operation. @@ -5391,7 +5391,7 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 dst_fla u_foreach_bit64(b, dst_flags) { - switch ((VkAccessFlags2)(1 << b)) { + switch ((VkAccessFlags2)BITFIELD64_BIT(b)) { case VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT: /* SMEM loads are used to read compute dispatch size in shaders */ if (!cmd_buffer->device->load_grid_size_from_user_sgpr)
