Module: Mesa Branch: main Commit: ea9d1cfb20c73a0c7cb17215389e23c8ff6ab40f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea9d1cfb20c73a0c7cb17215389e23c8ff6ab40f
Author: Rob Clark <[email protected]> Date: Sun Feb 12 09:57:50 2023 -0800 freedreno/a6xx: Fix sampler view rsc_seqno for X32_S8X24 Elsewhere we are comparing it against the seqno for the "primary" z32 buffer, so be consistent. Otherwise we'll think we need to re-validate every time the sampler view is bound. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21408> --- src/gallium/drivers/freedreno/a6xx/fd6_texture.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c index 7a005ee0fb8..39476626c7a 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c @@ -390,14 +390,15 @@ fd6_sampler_view_update(struct fd_context *ctx, fd6_validate_format(ctx, rsc, cso->format); + so->seqno = seqno_next_u16(&fd6_context(ctx)->tex_seqno); + so->rsc_seqno = rsc->seqno; + if (format == PIPE_FORMAT_X32_S8X24_UINT) { rsc = rsc->stencil; format = rsc->b.b.format; } - so->seqno = seqno_next_u16(&fd6_context(ctx)->tex_seqno); so->ptr1 = rsc; - so->rsc_seqno = rsc->seqno; if (cso->target == PIPE_BUFFER) { uint8_t swiz[4] = {cso->swizzle_r, cso->swizzle_g, cso->swizzle_b,
