Module: Mesa Branch: main Commit: 2028f1caa38531dac05e32d614642a44e5693566 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2028f1caa38531dac05e32d614642a44e5693566
Author: Tapani Pälli <[email protected]> Date: Thu Feb 9 16:34:54 2023 +0200 anv: emit 3DSTATE_HS in cmd_buffer_flush_gfx_state Patch packs 3DSTATE_HS state during pipeline creation but it gets emitted only before 3DPRIMITIVE. We will later need this to implement a workaround. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308> --- src/intel/vulkan/anv_private.h | 1 + src/intel/vulkan/genX_cmd_buffer.c | 7 ++++ src/intel/vulkan/genX_pipeline.c | 74 ++++++++++++++++++++------------------ 3 files changed, 47 insertions(+), 35 deletions(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 4341172d517..17f64be338c 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -3145,6 +3145,7 @@ struct anv_graphics_pipeline { uint32_t wm[2]; uint32_t blend_state[1 + MAX_RTS * 2]; uint32_t streamout_state[5]; + uint32_t hs[9]; } gfx8; }; diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 0a2b17e0762..5b8b29d9510 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3522,6 +3522,13 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer *cmd_buffer) } } + if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) { + uint32_t *dw = + anv_batch_emitn(&cmd_buffer->batch, GENX(3DSTATE_HS_length), + GENX(3DSTATE_HS)); + memcpy(dw, &pipeline->gfx8.hs, sizeof(pipeline->gfx8.hs)); + } + if (any_dynamic_state_dirty || cmd_buffer->state.gfx.dirty) genX(cmd_buffer_flush_dynamic_state)(cmd_buffer); } diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 067bce0778f..3974dabcb15 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1311,56 +1311,60 @@ emit_3dstate_hs_ds(struct anv_graphics_pipeline *pipeline, const struct brw_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline); const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline); - anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_HS), hs) { - hs.Enable = true; - hs.StatisticsEnable = true; - hs.KernelStartPointer = tcs_bin->kernel.offset; - /* Wa_1606682166 */ - hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin); - hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count; + struct GENX(3DSTATE_HS) hs = { + GENX(3DSTATE_HS_header), + }; + + hs.Enable = true; + hs.StatisticsEnable = true; + hs.KernelStartPointer = tcs_bin->kernel.offset; + /* Wa_1606682166 */ + hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin); + hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count; #if GFX_VER >= 12 - /* Wa_1604578095: - * - * Hang occurs when the number of max threads is less than 2 times - * the number of instance count. The number of max threads must be - * more than 2 times the number of instance count. - */ - assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances); + /* Wa_1604578095: + * + * Hang occurs when the number of max threads is less than 2 times + * the number of instance count. The number of max threads must be + * more than 2 times the number of instance count. + */ + assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances); #endif - hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1; - hs.IncludeVertexHandles = true; - hs.InstanceCount = tcs_prog_data->instances - 1; + hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1; + hs.IncludeVertexHandles = true; + hs.InstanceCount = tcs_prog_data->instances - 1; - hs.VertexURBEntryReadLength = 0; - hs.VertexURBEntryReadOffset = 0; - hs.DispatchGRFStartRegisterForURBData = - tcs_prog_data->base.base.dispatch_grf_start_reg & 0x1f; + hs.VertexURBEntryReadLength = 0; + hs.VertexURBEntryReadOffset = 0; + hs.DispatchGRFStartRegisterForURBData = + tcs_prog_data->base.base.dispatch_grf_start_reg & 0x1f; #if GFX_VER >= 12 - hs.DispatchGRFStartRegisterForURBData5 = - tcs_prog_data->base.base.dispatch_grf_start_reg >> 5; + hs.DispatchGRFStartRegisterForURBData5 = + tcs_prog_data->base.base.dispatch_grf_start_reg >> 5; #endif #if GFX_VERx10 >= 125 - hs.ScratchSpaceBuffer = - get_scratch_surf(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin); + hs.ScratchSpaceBuffer = + get_scratch_surf(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin); #else - hs.PerThreadScratchSpace = get_scratch_space(tcs_bin); - hs.ScratchSpaceBasePointer = - get_scratch_address(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin); + hs.PerThreadScratchSpace = get_scratch_space(tcs_bin); + hs.ScratchSpaceBasePointer = + get_scratch_address(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin); #endif #if GFX_VER == 12 - /* Patch Count threshold specifies the maximum number of patches that - * will be accumulated before a thread dispatch is forced. - */ - hs.PatchCountThreshold = tcs_prog_data->patch_count_threshold; + /* Patch Count threshold specifies the maximum number of patches that + * will be accumulated before a thread dispatch is forced. + */ + hs.PatchCountThreshold = tcs_prog_data->patch_count_threshold; #endif - hs.DispatchMode = tcs_prog_data->base.dispatch_mode; - hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id; - } + hs.DispatchMode = tcs_prog_data->base.dispatch_mode; + hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id; + + GENX(3DSTATE_HS_pack)(NULL, pipeline->gfx8.hs, &hs); anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_DS), ds) { ds.Enable = true;
