Module: Mesa Branch: main Commit: 8c6d741e26375129602e1e40d0eda46b765f418f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c6d741e26375129602e1e40d0eda46b765f418f
Author: Connor Abbott <[email protected]> Date: Mon Oct 17 16:22:52 2022 +0200 freedreno/a6xx: Rename CP_CSQ_IB*_STAT These don't correspond to the a3xx *_STAT registers, which we're about to add so we need to rename them. The closest analogue is CP_CSQ_AVAIL, although the sense is inverted (and we're not sure what the low 16 bits are about). Also, the a3xx distinction between CSQ and STQ doesn't exist anymore so don't use these outdated terms. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551> --- src/freedreno/.gitlab-ci/reference/crash.log | 6 +++--- src/freedreno/decode/crashdec.c | 4 ++-- src/freedreno/registers/adreno/a6xx.xml | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log index 3bee2b615ee..5a37ab02b79 100644 --- a/src/freedreno/.gitlab-ci/reference/crash.log +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -752,10 +752,10 @@ registers: 00000000 CP_MRB_DWORDS: 0 00000000 CP_VSD_DWORDS: 0 000f0004 0x948: 000f0004 - 00060002 CP_CSQ_IB1_STAT: { REM = 0x6 | 0x2 } - 00000000 CP_CSQ_IB2_STAT: { REM = 0 } + 00060002 CP_ROQ_AVAIL_IB1: { REM = 0x6 | 0x2 } + 00000000 CP_ROQ_AVAIL_IB2: { REM = 0 } 00000000 0x94b: 00000000 - 00000000 CP_MRQ_MRB_STAT: { REM = 0 } + 00000000 CP_ROQ_AVAIL_MRB: { REM = 0 } 00000000 0x94d: 00000000 00305efe CP_ALWAYS_ON_COUNTER: 0x305efe 00225162 0x982: 00225162 diff --git a/src/freedreno/decode/crashdec.c b/src/freedreno/decode/crashdec.c index 3110dc8e1a2..b1df32d69ff 100644 --- a/src/freedreno/decode/crashdec.c +++ b/src/freedreno/decode/crashdec.c @@ -359,8 +359,8 @@ dump_cmdstream(void) * by name rather than hard-coding this. */ if (is_a6xx()) { - options.ibs[1].rem += regval("CP_CSQ_IB1_STAT") >> 16; - options.ibs[2].rem += regval("CP_CSQ_IB2_STAT") >> 16; + options.ibs[1].rem += regval("CP_ROQ_AVAIL_IB1") >> 16; + options.ibs[2].rem += regval("CP_ROQ_AVAIL_IB2") >> 16; } printf("IB1: %" PRIx64 ", %u\n", options.ibs[1].base, options.ibs[1].rem); diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index 9f801a20c61..6a30c705d52 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -1098,15 +1098,15 @@ to upconvert to 32b float internally? There are probably similar registers for RB and SDS, teasing out SDS will take a slightly better test case.. --> - <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT"> + <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1"> <doc>number of remaining dwords incl current dword being consumed?</doc> <bitfield name="REM" low="16" high="31"/> </reg32> - <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT"> + <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2"> <doc>number of remaining dwords incl current dword being consumed?</doc> <bitfield name="REM" low="16" high="31"/> </reg32> - <reg32 offset="0x094c" name="CP_MRQ_MRB_STAT"> + <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB"> <doc>number of dwords that have already been read but haven't been consumed by $addr</doc> <bitfield name="REM" low="16" high="31"/> </reg32>
