Module: Mesa Branch: main Commit: ce7225c0f90abacc8dfc22d08d2a95cdde2d81cc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce7225c0f90abacc8dfc22d08d2a95cdde2d81cc
Author: Connor Abbott <[email protected]> Date: Mon Oct 17 17:57:03 2022 +0200 freedreno/a6xx: Fill in ROQ status registers We had a bunch of registers only defined for some parts of ROQ but now that we know the pattern for ROQ-related registers it's easy to fill in the rest. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551> --- src/freedreno/.gitlab-ci/reference/crash.log | 12 ++++++------ src/freedreno/registers/adreno/a6xx.xml | 20 ++++++++++++++++---- 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log index aa239193329..492f398f73a 100644 --- a/src/freedreno/.gitlab-ci/reference/crash.log +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -746,17 +746,17 @@ registers: 00b000b0 CP_ROQ_MRB_STAT: { RPTR = 0xb0 | WPTR = 0xb0 } 00d800d8 CP_ROQ_VSD_STAT: { RPTR = 0xd8 | WPTR = 0xd8 } 0000007f 0x942: 0000007f - 0000000c 0x943: 0000000c - 00000000 0x944: 00000000 - 00000000 0x945: 00000000 + 0000000c CP_IB1_DWORDS: 0xc + 00000000 CP_IB2_DWORDS: 0 + 00000000 CP_SDS_DWORDS: 0 00000000 CP_MRB_DWORDS: 0 00000000 CP_VSD_DWORDS: 0 - 000f0004 0x948: 000f0004 + 000f0004 CP_ROQ_AVAIL_RB: { REM = 0xf | 0x4 } 00060002 CP_ROQ_AVAIL_IB1: { REM = 0x6 | 0x2 } 00000000 CP_ROQ_AVAIL_IB2: { REM = 0 } - 00000000 0x94b: 00000000 + 00000000 CP_ROQ_AVAIL_SDS: { REM = 0 } 00000000 CP_ROQ_AVAIL_MRB: { REM = 0 } - 00000000 0x94d: 00000000 + 00000000 CP_ROQ_AVAIL_VSD: { REM = 0 } 00305efe CP_ALWAYS_ON_COUNTER: 0x305efe 00225162 0x982: 00225162 00000000 0x983: 00000000 diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index b5c9e6f6666..4ba87ba716d 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -1101,12 +1101,16 @@ to upconvert to 32b float internally? <reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/> <reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/> + <reg32 offset="0x0943" name="CP_IB1_DWORDS"/> + <reg32 offset="0x0944" name="CP_IB2_DWORDS"/> + <reg32 offset="0x0945" name="CP_SDS_DWORDS"/> <reg32 offset="0x0946" name="CP_MRB_DWORDS"/> <reg32 offset="0x0947" name="CP_VSD_DWORDS"/> - <!-- - There are probably similar registers for RB and SDS, teasing out SDS will - take a slightly better test case.. - --> + + <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB"> + <doc>number of remaining dwords incl current dword being consumed?</doc> + <bitfield name="REM" low="16" high="31"/> + </reg32> <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1"> <doc>number of remaining dwords incl current dword being consumed?</doc> <bitfield name="REM" low="16" high="31"/> @@ -1115,10 +1119,18 @@ to upconvert to 32b float internally? <doc>number of remaining dwords incl current dword being consumed?</doc> <bitfield name="REM" low="16" high="31"/> </reg32> + <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS"> + <doc>number of remaining dwords incl current dword being consumed?</doc> + <bitfield name="REM" low="16" high="31"/> + </reg32> <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB"> <doc>number of dwords that have already been read but haven't been consumed by $addr</doc> <bitfield name="REM" low="16" high="31"/> </reg32> + <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD"> + <doc>number of remaining dwords incl current dword being consumed?</doc> + <bitfield name="REM" low="16" high="31"/> + </reg32> <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/> <reg32 offset="0x098D" name="CP_AHB_CNTL"/> <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
