Module: Mesa Branch: main Commit: 96c832c47e3384069c0eef7c45aeb032990ef67e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96c832c47e3384069c0eef7c45aeb032990ef67e
Author: Faith Ekstrand <[email protected]> Date: Tue Feb 21 08:39:30 2023 -0600 spirv: Always emit deref_buffer_array_length intrinsics All the drivers have been converted to setting this option now except imagination and they don't support SSBOs yet. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3993 Reviewed-by: Caio Oliveira <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446> --- src/amd/vulkan/radv_shader.c | 1 - src/broadcom/vulkan/v3dv_pipeline.c | 1 - src/compiler/spirv/nir_spirv.h | 5 --- src/compiler/spirv/spirv2nir.c | 1 - src/compiler/spirv/vtn_variables.c | 48 ++++++--------------------- src/freedreno/vulkan/tu_shader.c | 1 - src/gallium/frontends/lavapipe/lvp_pipeline.c | 1 - src/intel/vulkan/anv_pipeline.c | 1 - src/intel/vulkan_hasvk/anv_pipeline.c | 1 - src/mesa/main/glspirv.c | 1 - src/microsoft/spirv_to_dxil/dxil_spirv_nir.c | 7 ---- src/panfrost/vulkan/panvk_vX_shader.c | 1 - 12 files changed, 11 insertions(+), 58 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 3908a03baa9..b116e642a4b 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -762,7 +762,6 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_ .push_const_addr_format = nir_address_format_logical, .shared_addr_format = nir_address_format_32bit_offset, .constant_addr_format = nir_address_format_64bit_global, - .use_deref_buffer_array_length = true, .debug = { .func = radv_spirv_nir_debug, diff --git a/src/broadcom/vulkan/v3dv_pipeline.c b/src/broadcom/vulkan/v3dv_pipeline.c index 50e6f78ff37..60b30e05a3a 100644 --- a/src/broadcom/vulkan/v3dv_pipeline.c +++ b/src/broadcom/vulkan/v3dv_pipeline.c @@ -176,7 +176,6 @@ static const struct spirv_to_nir_options default_spirv_options = { .workgroup_memory_explicit_layout = true, .image_read_without_format = true, }, - .use_deref_buffer_array_length = true, .ubo_addr_format = nir_address_format_32bit_index_offset, .ssbo_addr_format = nir_address_format_32bit_index_offset, .phys_ssbo_addr_format = nir_address_format_2x32bit_global, diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h index 7a2b1763772..d4668cf3d17 100644 --- a/src/compiler/spirv/nir_spirv.h +++ b/src/compiler/spirv/nir_spirv.h @@ -65,11 +65,6 @@ struct spirv_to_nir_options { /* Create a nir library. */ bool create_library; - /* Whether to use nir_intrinsic_deref_buffer_array_length intrinsic instead - * of nir_intrinsic_get_ssbo_size to lower OpArrayLength. - */ - bool use_deref_buffer_array_length; - /* Initial value for shader_info::float_controls_execution_mode, * indicates hardware requirements rather than shader author intent */ diff --git a/src/compiler/spirv/spirv2nir.c b/src/compiler/spirv/spirv2nir.c index c473bf2c8d7..1ea7434350c 100644 --- a/src/compiler/spirv/spirv2nir.c +++ b/src/compiler/spirv/spirv2nir.c @@ -162,7 +162,6 @@ int main(int argc, char **argv) struct spirv_to_nir_options spirv_opts = { .environment = env, - .use_deref_buffer_array_length = env == NIR_SPIRV_OPENGL, }; if (shader_stage == MESA_SHADER_KERNEL) { diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 2cf4da6c0b5..bf3c86748ca 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -2646,46 +2646,20 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode, "OpArrayLength must reference the last memeber of the " "structure and that must be an array"); - if (b->options->use_deref_buffer_array_length) { - struct vtn_access_chain chain = { - .length = 1, - .link = { - { .mode = vtn_access_mode_literal, .id = field }, - } - }; - struct vtn_pointer *array = vtn_pointer_dereference(b, ptr, &chain); - - nir_ssa_def *array_length = - nir_build_deref_buffer_array_length(&b->nb, 32, - vtn_pointer_to_ssa(b, array), - .access=ptr->access | ptr->type->access); - - vtn_push_nir_ssa(b, w[2], array_length); - } else { - const uint32_t offset = ptr->type->offsets[field]; - const uint32_t stride = ptr->type->members[field]->stride; - - if (!ptr->block_index) { - struct vtn_access_chain chain = { - .length = 0, - }; - ptr = vtn_pointer_dereference(b, ptr, &chain); - vtn_assert(ptr->block_index); + struct vtn_access_chain chain = { + .length = 1, + .link = { + { .mode = vtn_access_mode_literal, .id = field }, } + }; + struct vtn_pointer *array = vtn_pointer_dereference(b, ptr, &chain); - nir_ssa_def *buf_size = nir_get_ssbo_size(&b->nb, ptr->block_index, - .access=ptr->access | ptr->type->access); - - /* array_length = max(buffer_size - offset, 0) / stride */ - nir_ssa_def *array_length = - nir_udiv_imm(&b->nb, - nir_usub_sat(&b->nb, - buf_size, - nir_imm_int(&b->nb, offset)), - stride); + nir_ssa_def *array_length = + nir_build_deref_buffer_array_length(&b->nb, 32, + vtn_pointer_to_ssa(b, array), + .access=ptr->access | ptr->type->access); - vtn_push_nir_ssa(b, w[2], array_length); - } + vtn_push_nir_ssa(b, w[2], array_length); break; } diff --git a/src/freedreno/vulkan/tu_shader.c b/src/freedreno/vulkan/tu_shader.c index 575d8032c80..1f414f87c10 100644 --- a/src/freedreno/vulkan/tu_shader.c +++ b/src/freedreno/vulkan/tu_shader.c @@ -26,7 +26,6 @@ tu_spirv_to_nir(struct tu_device *dev, { /* TODO these are made-up */ const struct spirv_to_nir_options spirv_options = { - .use_deref_buffer_array_length = true, .ubo_addr_format = nir_address_format_vec2_index_32bit_offset, .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset, diff --git a/src/gallium/frontends/lavapipe/lvp_pipeline.c b/src/gallium/frontends/lavapipe/lvp_pipeline.c index 943c3b98169..1288223c031 100644 --- a/src/gallium/frontends/lavapipe/lvp_pipeline.c +++ b/src/gallium/frontends/lavapipe/lvp_pipeline.c @@ -408,7 +408,6 @@ lvp_shader_compile_to_ir(struct lvp_pipeline *pipeline, .float16 = true, .demote_to_helper_invocation = true, }, - .use_deref_buffer_array_length = true, .ubo_addr_format = nir_address_format_32bit_index_offset, .ssbo_addr_format = nir_address_format_32bit_index_offset, .phys_ssbo_addr_format = nir_address_format_64bit_global, diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 4f0c8858e25..898495f9ac5 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -208,7 +208,6 @@ anv_shader_stage_to_nir(struct anv_device *device, .workgroup_memory_explicit_layout = true, .fragment_shading_rate = pdevice->info.ver >= 11, }, - .use_deref_buffer_array_length = true, .ubo_addr_format = anv_nir_ubo_addr_format(pdevice, device->vk.enabled_features.robustBufferAccess), .ssbo_addr_format = diff --git a/src/intel/vulkan_hasvk/anv_pipeline.c b/src/intel/vulkan_hasvk/anv_pipeline.c index 21fe0d2f246..f88884faa14 100644 --- a/src/intel/vulkan_hasvk/anv_pipeline.c +++ b/src/intel/vulkan_hasvk/anv_pipeline.c @@ -114,7 +114,6 @@ anv_shader_stage_to_nir(struct anv_device *device, .vk_memory_model_device_scope = true, .workgroup_memory_explicit_layout = true, }, - .use_deref_buffer_array_length = true, .ubo_addr_format = anv_nir_ubo_addr_format(pdevice, device->vk.enabled_features.robustBufferAccess), .ssbo_addr_format = diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c index 126f53d1cfb..48649a4a187 100644 --- a/src/mesa/main/glspirv.c +++ b/src/mesa/main/glspirv.c @@ -243,7 +243,6 @@ _mesa_spirv_to_nir(struct gl_context *ctx, const struct spirv_to_nir_options spirv_options = { .environment = NIR_SPIRV_OPENGL, - .use_deref_buffer_array_length = true, .subgroup_size = SUBGROUP_SIZE_UNIFORM, .caps = ctx->Const.SpirVCapabilities, .ubo_addr_format = nir_address_format_32bit_index_offset, diff --git a/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c b/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c index 7facbb77da8..41f1e248669 100644 --- a/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c +++ b/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c @@ -53,13 +53,6 @@ spirv_to_nir_options = { .ssbo_addr_format = nir_address_format_32bit_index_offset, .shared_addr_format = nir_address_format_32bit_offset, - /* use_deref_buffer_array_length + nir_lower_explicit_io force - * get_ssbo_size to take in the return from load_vulkan_descriptor - * instead of vulkan_resource_index. This makes it much easier to - * get the DXIL handle for the SSBO. - */ - .use_deref_buffer_array_length = true, - .min_ubo_alignment = 256, /* D3D12_CONSTANT_BUFFER_DATA_PLACEMENT_ALIGNMENT */ .min_ssbo_alignment = 16, /* D3D12_RAW_UAV_SRV_BYTE_ALIGNMENT */ }; diff --git a/src/panfrost/vulkan/panvk_vX_shader.c b/src/panfrost/vulkan/panvk_vX_shader.c index ac6853a441f..fde8445ca98 100644 --- a/src/panfrost/vulkan/panvk_vX_shader.c +++ b/src/panfrost/vulkan/panvk_vX_shader.c @@ -241,7 +241,6 @@ panvk_per_arch(shader_create)(struct panvk_device *dev, .caps = { .variable_pointers = true, }, - .use_deref_buffer_array_length = true, .ubo_addr_format = nir_address_format_32bit_index_offset, .ssbo_addr_format = dev->vk.enabled_features.robustBufferAccess ? nir_address_format_64bit_bounded_global :
