Module: Mesa Branch: main Commit: 1c5c2f77c3a8a80c81ef693b67f8f707871a28ca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c5c2f77c3a8a80c81ef693b67f8f707871a28ca
Author: Georg Lehmann <[email protected]> Date: Thu Feb 23 11:35:13 2023 +0100 aco: use and swizzle mask in dpp quad perm Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21412> --- src/amd/compiler/aco_instruction_selection.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 9a47f3d573f..2d0134373c5 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -253,10 +253,10 @@ emit_masked_swizzle(isel_context* ctx, Builder& bld, Temp src, unsigned mask) * because DPP16 supports modifiers and v_permlane * can't be folded into valu instructions. */ - if (and_mask == 0x1f && or_mask < 4 && xor_mask < 4) { + if ((and_mask & 0x1c) == 0x1c && or_mask < 4 && xor_mask < 4) { unsigned res[4] = {0, 1, 2, 3}; for (unsigned i = 0; i < 4; i++) - res[i] = ((res[i] | or_mask) ^ xor_mask) & 0x3; + res[i] = (((res[i] & and_mask) | or_mask) ^ xor_mask) & 0x3; dpp_ctrl = dpp_quad_perm(res[0], res[1], res[2], res[3]); } else if (and_mask == 0x1f && !or_mask && xor_mask == 8) { dpp_ctrl = dpp_row_rr(8);
