Module: Mesa Branch: main Commit: 901bc6d53ca24d0128a925d2efb96084f8b9ec81 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=901bc6d53ca24d0128a925d2efb96084f8b9ec81
Author: Caio Oliveira <[email protected]> Date: Sun Feb 26 21:57:49 2023 -0800 pan/midgard: Handle nir_intrinsic_scoped_barrier in Midgard compiler Behave the same as the existing more specific barrier intrinsics. Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3339> --- src/panfrost/midgard/midgard_compile.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 94a59adabd2..6a1db58333b 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -2120,6 +2120,22 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) schedule_barrier(ctx); break; + case nir_intrinsic_scoped_barrier: + if (nir_intrinsic_execution_scope(instr) != NIR_SCOPE_NONE) { + schedule_barrier(ctx); + emit_control_barrier(ctx); + schedule_barrier(ctx); + } else if (nir_intrinsic_memory_scope(instr) != NIR_SCOPE_NONE) { + /* Midgard doesn't seem to want special handling, though we do need to + * take care when scheduling to avoid incorrect reordering. + * + * Note this is an "else if" since the handling for the execution scope + * case already covers the case when both scopes are present. + */ + schedule_barrier(ctx); + } + break; + ATOMIC_CASE(ctx, instr, add, add); ATOMIC_CASE(ctx, instr, and, and); ATOMIC_CASE(ctx, instr, comp_swap, cmpxchg);
