Module: Mesa Branch: main Commit: efde1917c933a293497e738616e18a91b02026d7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=efde1917c933a293497e738616e18a91b02026d7
Author: Lionel Landwerlin <[email protected]> Date: Fri Mar 10 16:11:56 2023 +0200 intel/fs: don't SEND messages as partial writes For instance, to load uniform data with the LSC we usually rely on tranpose messages which have to execute in SIMD1. Those end up being considered as partial writes so within loops their life span spread to the whole loop, increasing register pressure. Signed-off-by: Lionel Landwerlin <[email protected]> Cc: mesa-stable Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21867> --- src/intel/compiler/brw_fs.cpp | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index b2739dccc8f..054716a7ea4 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -641,10 +641,18 @@ fs_visitor::limit_dispatch_width(unsigned n, const char *msg) bool fs_inst::is_partial_write() const { - return ((this->predicate && this->opcode != BRW_OPCODE_SEL) || - (this->exec_size * type_sz(this->dst.type)) < 32 || - !this->dst.is_contiguous() || - this->dst.offset % REG_SIZE != 0); + if (this->predicate && this->opcode != BRW_OPCODE_SEL) + return true; + + if (this->dst.offset % REG_SIZE != 0) + return true; + + /* SEND instructions always write whole registers */ + if (this->opcode == SHADER_OPCODE_SEND) + return false; + + return this->exec_size * type_sz(this->dst.type) < 32 || + !this->dst.is_contiguous(); } unsigned
