Module: Mesa Branch: main Commit: 84197bc0a4fa770e5ebdab8149e4baa5b2d400d5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=84197bc0a4fa770e5ebdab8149e4baa5b2d400d5
Author: Kenneth Graunke <[email protected]> Date: Thu Mar 16 14:53:50 2023 -0700 intel/vec4: Retype texture/sampler indexes to UD generate_tex() asserts that sampler_index.type == UD, but commit 83fd7a5ed15 removed the uint temporary, which caused us to see D at some points. Really, either should be fine, but let's just put the UD retype back. This fixes a ton of things in crocus. Fixes: 83fd7a5ed15 ("intel: Use nir_lower_tex_options::lower_index_to_offset") Reviewed-by: Emma Anholt <[email protected]> Reviewed-by: Faith Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21974> --- src/intel/compiler/brw_vec4_nir.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 5f93f0a24e2..32b0a3af5d5 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1949,13 +1949,15 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) case nir_tex_src_texture_offset: { assert(texture_reg.is_zero()); - texture_reg = emit_uniformize(get_nir_src(instr->src[i].src, 1)); + texture_reg = emit_uniformize(get_nir_src(instr->src[i].src, + BRW_REGISTER_TYPE_UD, 1)); break; } case nir_tex_src_sampler_offset: { assert(sampler_reg.is_zero()); - sampler_reg = emit_uniformize(get_nir_src(instr->src[i].src, 1)); + sampler_reg = emit_uniformize(get_nir_src(instr->src[i].src, + BRW_REGISTER_TYPE_UD, 1)); break; }
