Module: Mesa Branch: main Commit: 609edd6e96facc8efeeae888665a5c5e8783707e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=609edd6e96facc8efeeae888665a5c5e8783707e
Author: Samuel Pitoiset <[email protected]> Date: Fri Mar 24 14:15:26 2023 +0100 radv: copy the multisample state to radv_cmd_state To avoid relying on the pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22110> --- src/amd/vulkan/radv_cmd_buffer.c | 14 +++++++++++--- src/amd/vulkan/radv_private.h | 12 +++++++----- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 337368a5405..56609e7aae9 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -942,15 +942,14 @@ radv_get_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) static ALWAYS_INLINE unsigned radv_get_ps_iter_samples(struct radv_cmd_buffer *cmd_buffer) { - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; const struct radv_rendering_state *render = &cmd_buffer->state.render; unsigned ps_iter_samples = 1; - if (pipeline->ms.sample_shading_enable) { + if (cmd_buffer->state.ms.sample_shading_enable) { unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); unsigned color_samples = MAX2(render->color_samples, rasterization_samples); - ps_iter_samples = ceilf(pipeline->ms.min_sample_shading * color_samples); + ps_iter_samples = ceilf(cmd_buffer->state.ms.min_sample_shading * color_samples); ps_iter_samples = util_next_power_of_two(ps_iter_samples); } @@ -6247,6 +6246,13 @@ radv_bind_vs_input_state(struct radv_cmd_buffer *cmd_buffer, cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT; } +static void +radv_bind_multisample_state(struct radv_cmd_buffer *cmd_buffer, + const struct radv_multisample_state *ms) +{ + cmd_buffer->state.ms = *ms; +} + static void radv_bind_pre_rast_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *shader) { @@ -6493,6 +6499,8 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline radv_bind_mesh_shader(cmd_buffer, graphics_pipeline->base.shaders[MESA_SHADER_MESH]); if (graphics_pipeline->base.shaders[MESA_SHADER_TASK]) radv_bind_task_shader(cmd_buffer, graphics_pipeline->base.shaders[MESA_SHADER_TASK]); + + radv_bind_multisample_state(cmd_buffer, &graphics_pipeline->ms); break; } default: diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 3b7e5b890d4..87b7707ee76 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1571,6 +1571,11 @@ enum rgp_flush_bits { RGP_FLUSH_INVAL_L1 = 0x8000, }; +struct radv_multisample_state { + bool sample_shading_enable; + float min_sample_shading; +}; + struct radv_cmd_state { /* Vertex descriptors */ uint64_t vb_va; @@ -1683,6 +1688,8 @@ struct radv_cmd_state { /* Binning state */ unsigned last_pa_sc_binner_cntl_0; + + struct radv_multisample_state ms; }; struct radv_cmd_buffer_upload { @@ -2094,11 +2101,6 @@ enum { extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS]; unsigned radv_format_meta_fs_key(struct radv_device *device, VkFormat format); -struct radv_multisample_state { - bool sample_shading_enable; - float min_sample_shading; -}; - struct radv_vrs_state { uint32_t pa_cl_vrs_cntl; };
