Module: Mesa Branch: main Commit: e61d68ac8aea46dfd03369af8ecd91add229f834 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e61d68ac8aea46dfd03369af8ecd91add229f834
Author: Samuel Pitoiset <[email protected]> Date: Fri Mar 24 11:03:42 2023 +0100 radv: move {esgs,gsvs}_ring_size to radv_legacy_gs_info To update the ring info when a geometry shader is bound. Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22134> --- src/amd/vulkan/radv_cmd_buffer.c | 10 +++++----- src/amd/vulkan/radv_pipeline.c | 42 --------------------------------------- src/amd/vulkan/radv_private.h | 2 -- src/amd/vulkan/radv_shader.h | 2 ++ src/amd/vulkan/radv_shader_info.c | 36 +++++++++++++++++++++++++++++++++ 5 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f200137f665..aaa4fbe17f9 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6323,6 +6323,11 @@ static void radv_bind_geometry_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *gs) { radv_bind_pre_rast_shader(cmd_buffer, gs); + + cmd_buffer->esgs_ring_size_needed = + MAX2(cmd_buffer->esgs_ring_size_needed, gs->info.gs_ring_info.esgs_ring_size); + cmd_buffer->gsvs_ring_size_needed = + MAX2(cmd_buffer->gsvs_ring_size_needed, gs->info.gs_ring_info.gsvs_ring_size); } static void @@ -6467,11 +6472,6 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline radv_bind_vs_input_state(cmd_buffer, graphics_pipeline); - if (graphics_pipeline->esgs_ring_size > cmd_buffer->esgs_ring_size_needed) - cmd_buffer->esgs_ring_size_needed = graphics_pipeline->esgs_ring_size; - if (graphics_pipeline->gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed) - cmd_buffer->gsvs_ring_size_needed = graphics_pipeline->gsvs_ring_size; - cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed, pipeline->scratch_bytes_per_wave); cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted, pipeline->max_waves); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9c3136ae78f..5164c090ee2 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1411,42 +1411,6 @@ gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, S_030980_OVERSUB_EN(oversub_pc_lines > 0) | S_030980_NUM_PC_LINES(oversub_pc_lines - 1)); } -static void -radv_pipeline_init_legacy_gs_ring_info(const struct radv_device *device, - struct radv_graphics_pipeline *pipeline, - const struct radv_legacy_gs_info *gs) -{ - const struct radv_physical_device *pdevice = device->physical_device; - unsigned num_se = pdevice->rad_info.max_se; - unsigned wave_size = 64; - unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */ - /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16. - * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). - */ - unsigned gs_vertex_reuse = (pdevice->rad_info.gfx_level >= GFX8 ? 32 : 16) * num_se; - unsigned alignment = 256 * num_se; - /* The maximum size is 63.999 MB per SE. */ - unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; - struct radv_shader_info *gs_info = &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info; - - /* Calculate the minimum size. */ - unsigned min_esgs_ring_size = - align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse * wave_size, alignment); - /* These are recommended sizes, not minimum sizes. */ - unsigned esgs_ring_size = - max_gs_waves * 2 * wave_size * gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in; - unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs_info->gs.max_gsvs_emit_size; - - min_esgs_ring_size = align(min_esgs_ring_size, alignment); - esgs_ring_size = align(esgs_ring_size, alignment); - gsvs_ring_size = align(gsvs_ring_size, alignment); - - if (pdevice->rad_info.gfx_level <= GFX8) - pipeline->esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); - - pipeline->gsvs_ring_size = MIN2(gsvs_ring_size, max_size); -} - struct radv_shader * radv_get_shader(const struct radv_pipeline *pipeline, gl_shader_stage stage) { @@ -4965,12 +4929,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv pipeline->col_format_non_compacted = V_028714_SPI_SHADER_32_R; } - if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) { - struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY]; - - radv_pipeline_init_legacy_gs_ring_info(device, pipeline, &gs->info.gs_ring_info); - } - if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) radv_pipeline_init_vertex_input_state(device, pipeline, &state); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index bc8651837c3..2998ed3bef7 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2210,8 +2210,6 @@ struct radv_graphics_pipeline { uint8_t vtx_emit_num; - unsigned esgs_ring_size; - unsigned gsvs_ring_size; uint32_t vtx_base_sgpr; uint64_t dynamic_states; uint64_t needed_dynamic_state; diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 3c61cd206f2..fe0d79e032a 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -225,6 +225,8 @@ struct radv_legacy_gs_info { uint32_t vgt_gs_max_prims_per_subgroup; uint32_t vgt_esgs_ring_itemsize; uint32_t lds_size; + uint32_t esgs_ring_size; + uint32_t gsvs_ring_size; }; struct gfx10_ngg_info { diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index dfae34ca619..aff81f9280f 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -914,6 +914,40 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n } } +static void +radv_init_legacy_gs_ring_info(const struct radv_device *device, struct radv_shader_info *gs_info) +{ + const struct radv_physical_device *pdevice = device->physical_device; + struct radv_legacy_gs_info *gs_ring_info = &gs_info->gs_ring_info; + unsigned num_se = pdevice->rad_info.max_se; + unsigned wave_size = 64; + unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */ + /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16. + * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). + */ + unsigned gs_vertex_reuse = (pdevice->rad_info.gfx_level >= GFX8 ? 32 : 16) * num_se; + unsigned alignment = 256 * num_se; + /* The maximum size is 63.999 MB per SE. */ + unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; + + /* Calculate the minimum size. */ + unsigned min_esgs_ring_size = + align(gs_ring_info->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse * wave_size, alignment); + /* These are recommended sizes, not minimum sizes. */ + unsigned esgs_ring_size = + max_gs_waves * 2 * wave_size * gs_ring_info->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in; + unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs_info->gs.max_gsvs_emit_size; + + min_esgs_ring_size = align(min_esgs_ring_size, alignment); + esgs_ring_size = align(esgs_ring_size, alignment); + gsvs_ring_size = align(gsvs_ring_size, alignment); + + if (pdevice->rad_info.gfx_level <= GFX8) + gs_ring_info->esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); + + gs_ring_info->gsvs_ring_size = MIN2(gsvs_ring_size, max_size); +} + static void radv_get_legacy_gs_info(const struct radv_device *device, struct radv_pipeline_stage *es_stage, struct radv_pipeline_stage *gs_stage) @@ -1019,6 +1053,8 @@ radv_get_legacy_gs_info(const struct radv_device *device, struct radv_pipeline_s es_verts_per_subgroup, gs_inst_prims_in_subgroup); es_info->workgroup_size = workgroup_size; gs_info->workgroup_size = workgroup_size; + + radv_init_legacy_gs_ring_info(device, &gs_stage->info); } static void
