Module: Mesa Branch: main Commit: 3df1c4455e86653a4980c8d7ed54d844b14ce13e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3df1c4455e86653a4980c8d7ed54d844b14ce13e
Author: Qiang Yu <[email protected]> Date: Fri Feb 24 14:17:07 2023 +0800 ac/llvm: implement float16 nir_op_pack_(s|u)norm_2x16 Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21552> --- src/amd/llvm/ac_nir_to_llvm.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 166057395ad..129ec5f9eab 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -1127,11 +1127,29 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) ctx->ac.i32, ""); break; case nir_op_pack_snorm_2x16: - result = emit_pack_2x16(&ctx->ac, src[0], ac_build_cvt_pknorm_i16); - break; - case nir_op_pack_unorm_2x16: - result = emit_pack_2x16(&ctx->ac, src[0], ac_build_cvt_pknorm_u16); + case nir_op_pack_unorm_2x16: { + unsigned bit_size = instr->src[0].src.ssa->bit_size; + /* Only support 16 and 32bit. */ + assert(bit_size == 16 || bit_size == 32); + + LLVMValueRef data = src[0]; + /* Work around for pre-GFX9 GPU which don't have fp16 pknorm instruction. */ + if (bit_size == 16 && ctx->ac.gfx_level < GFX9) { + data = LLVMBuildFPExt(ctx->ac.builder, data, ctx->ac.v2f32, ""); + bit_size = 32; + } + + LLVMValueRef (*pack)(struct ac_llvm_context *ctx, LLVMValueRef args[2]); + if (bit_size == 32) { + pack = instr->op == nir_op_pack_snorm_2x16 ? + ac_build_cvt_pknorm_i16 : ac_build_cvt_pknorm_u16; + } else { + pack = instr->op == nir_op_pack_snorm_2x16 ? + ac_build_cvt_pknorm_i16_f16 : ac_build_cvt_pknorm_u16_f16; + } + result = emit_pack_2x16(&ctx->ac, data, pack); break; + } case nir_op_pack_uint_2x16: { LLVMValueRef comp[2];
