Module: Mesa Branch: main Commit: 69da1857933a214e4a2b50be98752b941238e157 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69da1857933a214e4a2b50be98752b941238e157
Author: Samuel Pitoiset <[email protected]> Date: Fri Mar 24 08:23:24 2023 +0100 radv: use the ES type to apply a workaround for NGG on GFX10 Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22095> --- src/amd/vulkan/radv_pipeline.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 598e7edf42d..e7c060e00c7 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3876,8 +3876,8 @@ radv_pipeline_emit_hw_ngg(const struct radv_device *device, struct radeon_cmdbuf * * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5 */ - if (pdevice->rad_info.gfx_level == GFX10 && - !radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL) && ngg_state->hw_max_esverts != 256) { + if (pdevice->rad_info.gfx_level == GFX10 && es_type != MESA_SHADER_TESS_EVAL && + ngg_state->hw_max_esverts != 256) { ge_cntl &= C_03096C_VERT_GRP_SIZE; if (ngg_state->hw_max_esverts > 5) {
