Module: Mesa Branch: main Commit: bbd124fd005e8b66311b426a61a640546d7e4cbb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbd124fd005e8b66311b426a61a640546d7e4cbb
Author: Alejandro Piñeiro <[email protected]> Date: Sun Apr 2 00:19:32 2023 +0200 v3dv/pipeline: use pipeline depth bias enabled to fill up CFG packet Even if the VkPipelineRasterizationStateCreateInfo sets depthBiasEnable, internally we comput if it is really makes sense, and use that to decide for example if we emit the Depth Offset packet. But we were not using this to enable Depth Bias through the depth offset enable field on the CFG packet. So in some tests we were enabling depth bias, but not emitting the packet to configure it, that seemed somewhat inconsistent. This didn't cause any issue so far, but let's be conservative. Reviewed-by: Iago Toral Quiroga <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22252> --- src/broadcom/vulkan/v3dv_pipeline.c | 3 ++- src/broadcom/vulkan/v3dvx_pipeline.c | 6 +++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/broadcom/vulkan/v3dv_pipeline.c b/src/broadcom/vulkan/v3dv_pipeline.c index e12bcfb04d5..04143e5f0c8 100644 --- a/src/broadcom/vulkan/v3dv_pipeline.c +++ b/src/broadcom/vulkan/v3dv_pipeline.c @@ -2966,11 +2966,12 @@ pipeline_init(struct v3dv_pipeline *pipeline, */ assert(!ds_info || !ds_info->depthBoundsTestEnable); + enable_depth_bias(pipeline, rs_info); + v3dv_X(device, pipeline_pack_state)(pipeline, cb_info, ds_info, rs_info, pv_info, ls_info, ms_info); - enable_depth_bias(pipeline, rs_info); pipeline_set_sample_mask(pipeline, ms_info); pipeline_set_sample_rate_shading(pipeline, ms_info); diff --git a/src/broadcom/vulkan/v3dvx_pipeline.c b/src/broadcom/vulkan/v3dvx_pipeline.c index ad904eb20b0..45aec26234f 100644 --- a/src/broadcom/vulkan/v3dvx_pipeline.c +++ b/src/broadcom/vulkan/v3dvx_pipeline.c @@ -164,7 +164,11 @@ pack_cfg_bits(struct v3dv_pipeline *pipeline, config.clockwise_primitives = rs_info ? rs_info->frontFace == VK_FRONT_FACE_COUNTER_CLOCKWISE : false; - config.enable_depth_offset = rs_info ? rs_info->depthBiasEnable: false; + /* Even if rs_info->depthBiasEnabled is true, we can decide to not + * enable it, like if there isn't a depth/stencil attachment with the + * pipeline. + */ + config.enable_depth_offset = pipeline->depth_bias.enabled; /* This is required to pass line rasterization tests in CTS while * exposing, at least, a minimum of 4-bits of subpixel precision
