Module: Mesa Branch: staging/23.0 Commit: d86beb2050c830ba50faf040c55b1d3e1a4726b5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d86beb2050c830ba50faf040c55b1d3e1a4726b5
Author: Lionel Landwerlin <[email protected]> Date: Wed Mar 29 11:06:13 2023 +0300 anv: implement recommended flush/wait of AUX-TT invalidation Signed-off-by: Lionel Landwerlin <[email protected]> Cc: mesa-stable Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22183> (cherry picked from commit 763854f7e306b61d1857b00f5d51e1b4d925a5f5) --- .pick_status.json | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 35 +++++++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 5ebbd3e90a5..00ded922446 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -2938,7 +2938,7 @@ "description": "anv: implement recommended flush/wait of AUX-TT invalidation", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 066817432a7..59d4a9ddf38 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1595,9 +1595,27 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, * "Driver must ensure that the engine is IDLE but ensure it doesn't * add extra flushes in the case it knows that the engine is already * IDLE." + * + * HSD 22012751911: SW Programming sequence when issuing aux invalidation: + * + * "Render target Cache Flush + L3 Fabric Flush + State Invalidation + CS Stall" + * + * Notice we don't set the L3 Fabric Flush here, because we have + * ANV_PIPE_END_OF_PIPE_SYNC_BIT which inserts a CS stall. The + * PIPE_CONTROL::L3 Fabric Flush documentation says : + * + * "L3 Fabric Flush will ensure all the pending transactions in the L3 + * Fabric are flushed to global observation point. HW does implicit L3 + * Fabric Flush on all stalling flushes (both explicit and implicit) + * and on PIPECONTROL having Post Sync Operation enabled." + * + * Therefore setting L3 Fabric Flush here would be redundant. */ - if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)) - bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT; + if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)) { + bits |= (ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT | + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_STATE_CACHE_INVALIDATE_BIT); + } /* If we're going to do an invalidate and we have a pending end-of-pipe * sync that has yet to be resolved, we do the end-of-pipe sync now. @@ -1816,6 +1834,19 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, lri.RegisterOffset = GENX(GFX_CCS_AUX_INV_num); lri.DataDWord = 1; } + /* HSD 22012751911: SW Programming sequence when issuing aux invalidation: + * + * "Poll Aux Invalidation bit once the invalidation is set + * (Register 4208 bit 0)" + */ + anv_batch_emit(batch, GENX(MI_SEMAPHORE_WAIT), sem) { + sem.CompareOperation = COMPARE_SAD_EQUAL_SDD; + sem.WaitMode = PollingMode; + sem.RegisterPollMode = true; + sem.SemaphoreDataDword = 0x0; + sem.SemaphoreAddress = + anv_address_from_u64(GENX(GFX_CCS_AUX_INV_num)); + } } #endif
