Module: Mesa Branch: main Commit: 981f512037ded3cb5ac189b9f8d5d25b9d274c59 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=981f512037ded3cb5ac189b9f8d5d25b9d274c59
Author: Samuel Pitoiset <[email protected]> Date: Wed Apr 5 12:05:10 2023 +0200 radv: emit the PS epilog after the graphics pipeline Otherwise, SPI_SHADER_PGM_RSRC1_PS is overwritten when the graphics pipeline is emitted. Fixes: 5c362cde33b ("radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs") Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22310> --- src/amd/vulkan/radv_cmd_buffer.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index fb6bff42ab3..880d060630a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -8870,11 +8870,10 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r bool pipeline_is_dirty) { const struct radv_device *device = cmd_buffer->device; + struct radv_shader_part *ps_epilog = NULL; bool late_scissor_emission; if (cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog) { - struct radv_shader_part *ps_epilog = NULL; - if (cmd_buffer->state.graphics_pipeline->ps_epilog) { ps_epilog = cmd_buffer->state.graphics_pipeline->ps_epilog; } else if ((cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline || @@ -8895,9 +8894,6 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r if (device->physical_device->rad_info.rbplus_allowed) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS; } - - if (ps_epilog) - radv_emit_ps_epilog_state(cmd_buffer, ps_epilog, pipeline_is_dirty); } if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RBPLUS) @@ -8925,6 +8921,9 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) radv_emit_graphics_pipeline(cmd_buffer); + if (ps_epilog) + radv_emit_ps_epilog_state(cmd_buffer, ps_epilog, pipeline_is_dirty); + /* This should be before the cmd_buffer->state.dirty is cleared * (excluding RADV_CMD_DIRTY_PIPELINE) and after * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
