Module: Mesa Branch: staging/23.0 Commit: 3e0dfb0017d566a1ab5f9f50a28fa0b9dff45a6d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e0dfb0017d566a1ab5f9f50a28fa0b9dff45a6d
Author: Timur Kristóf <[email protected]> Date: Thu Mar 30 00:33:17 2023 +0200 ac/nir: Store only lowest 8 bits for task draw ring DWORD3. When writing the draw ready bit, don't write the high 24 bits of DWORD3, because that is used by the HW for something else according to LLPC. Cc: mesa-stable Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22211> (cherry picked from commit 4683b21399df1cc20a02d36478fe4f4d8f743fd4) --- .pick_status.json | 2 +- src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index e12325320e6..44ccaeff8dd 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -229,7 +229,7 @@ "description": "ac/nir: Store only lowest 8 bits for task draw ring DWORD3.", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c index a0584abba23..5f320c5a77d 100644 --- a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c @@ -211,7 +211,7 @@ task_draw_ready_bit(nir_builder *b, nir_ssa_def *workgroup_index = task_workgroup_index(b, s); nir_ssa_def *idx = nir_iadd_nuw(b, ring_entry, workgroup_index); - return nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1)); + return nir_u2u8(b, nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1))); } static nir_ssa_def * @@ -288,9 +288,13 @@ lower_task_launch_mesh_workgroups(nir_builder *b, nir_ssa_def *x = nir_channel(b, dimensions, 0); nir_ssa_def *y = nir_channel(b, dimensions, 1); nir_ssa_def *z = nir_channel(b, dimensions, 2); - nir_ssa_def *rdy = task_draw_ready_bit(b, s); - nir_ssa_def *store_val = nir_vec4(b, x, y, z, rdy); - task_write_draw_ring(b, store_val, 0, s); + + /* Dispatch dimensions of mesh shader workgroups. */ + task_write_draw_ring(b, nir_vec3(b, x, y, z), 0, s); + /* Prevent the two stores from being reordered. */ + nir_scoped_memory_barrier(b, NIR_SCOPE_INVOCATION, NIR_MEMORY_RELEASE, nir_var_shader_out); + /* Ready bit, only write the low 8 bits. */ + task_write_draw_ring(b, task_draw_ready_bit(b, s), 12, s); } nir_pop_if(b, if_invocation_index_zero);
