Module: Mesa Branch: staging/23.0 Commit: 33e4fe697fdb8cbcd12c2c3cc8362dae82560f8f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33e4fe697fdb8cbcd12c2c3cc8362dae82560f8f
Author: Lionel Landwerlin <[email protected]> Date: Mon Apr 3 09:25:44 2023 +0300 intel/perf: fix OA format selection on MTL Anything Gfx12.5+ has a different format. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 90c86fe63e ("intel: add MTL performance metrics") Reviewed-by: José Roberto de Souza <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22257> (cherry picked from commit a88aedbfa5b620be844c0f5615d484c970ea66ac) --- .pick_status.json | 2 +- src/intel/perf/gen_perf.py | 7 +--- src/intel/perf/intel_perf_setup.h | 70 +++++++++++++++------------------------ 3 files changed, 29 insertions(+), 50 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index cf340f879fd..679119e8450 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -868,7 +868,7 @@ "description": "intel/perf: fix OA format selection on MTL", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "90c86fe63e94df7719081f86ebee4851ab3fd341" }, diff --git a/src/intel/perf/gen_perf.py b/src/intel/perf/gen_perf.py index dd158ffa8c1..4a8b78f4373 100644 --- a/src/intel/perf/gen_perf.py +++ b/src/intel/perf/gen_perf.py @@ -962,12 +962,7 @@ def main(): c("{\n") c_indent(3) - if gen.chipset == "hsw": - c("struct intel_perf_query_info *query = hsw_query_alloc(perf, %u);\n" % len(counters)) - elif gen.chipset.startswith("acm"): - c("struct intel_perf_query_info *query = xehp_query_alloc(perf, %u);\n" % len(counters)) - else: - c("struct intel_perf_query_info *query = bdw_query_alloc(perf, %u);\n" % len(counters)) + c("struct intel_perf_query_info *query = intel_query_alloc(perf, %u);\n" % len(counters)) c("\n") c("query->name = \"" + set.name + "\";\n") c("query->symbol_name = \"" + set.symbol_name + "\";\n") diff --git a/src/intel/perf/intel_perf_setup.h b/src/intel/perf/intel_perf_setup.h index cfa5a3c75d7..25e697c2d7e 100644 --- a/src/intel/perf/intel_perf_setup.h +++ b/src/intel/perf/intel_perf_setup.h @@ -38,52 +38,36 @@ intel_query_alloc(struct intel_perf_config *perf, int ncounters) query->n_counters = 0; query->oa_metrics_set_id = 0; /* determined at runtime, via sysfs */ query->counters = rzalloc_array(query, struct intel_perf_query_counter, ncounters); - return query; -} - -static struct intel_perf_query_info * -hsw_query_alloc(struct intel_perf_config *perf, int ncounters) -{ - struct intel_perf_query_info *query = intel_query_alloc(perf, ncounters); - query->oa_format = I915_OA_FORMAT_A45_B8_C8; - /* Accumulation buffer offsets... */ - query->gpu_time_offset = 0; - query->a_offset = query->gpu_time_offset + 1; - query->b_offset = query->a_offset + 45; - query->c_offset = query->b_offset + 8; - query->perfcnt_offset = query->c_offset + 8; - query->rpstat_offset = query->perfcnt_offset + 2; - return query; -} -static struct intel_perf_query_info * -bdw_query_alloc(struct intel_perf_config *perf, int ncounters) -{ - struct intel_perf_query_info *query = intel_query_alloc(perf, ncounters); - query->oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8; /* Accumulation buffer offsets... */ - query->gpu_time_offset = 0; - query->gpu_clock_offset = query->gpu_time_offset + 1; - query->a_offset = query->gpu_clock_offset + 1; - query->b_offset = query->a_offset + 36; - query->c_offset = query->b_offset + 8; - query->perfcnt_offset = query->c_offset + 8; - query->rpstat_offset = query->perfcnt_offset + 2; - return query; -} + if (perf->devinfo.verx10 <= 75) { + query->oa_format = I915_OA_FORMAT_A45_B8_C8; + query->gpu_time_offset = 0; + query->a_offset = query->gpu_time_offset + 1; + query->b_offset = query->a_offset + 45; + query->c_offset = query->b_offset + 8; + query->perfcnt_offset = query->c_offset + 8; + query->rpstat_offset = query->perfcnt_offset + 2; + } else if (perf->devinfo.verx10 <= 120) { + query->oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8; + query->gpu_time_offset = 0; + query->gpu_clock_offset = query->gpu_time_offset + 1; + query->a_offset = query->gpu_clock_offset + 1; + query->b_offset = query->a_offset + 36; + query->c_offset = query->b_offset + 8; + query->perfcnt_offset = query->c_offset + 8; + query->rpstat_offset = query->perfcnt_offset + 2; + } else { + query->oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8; + query->gpu_time_offset = 0; + query->gpu_clock_offset = query->gpu_time_offset + 1; + query->a_offset = query->gpu_clock_offset + 1; + query->b_offset = query->a_offset + 38; + query->c_offset = query->b_offset + 8; + query->perfcnt_offset = query->c_offset + 8; + query->rpstat_offset = query->perfcnt_offset + 2; + } -static struct intel_perf_query_info * -xehp_query_alloc(struct intel_perf_config *perf, int ncounters) -{ - struct intel_perf_query_info *query = intel_query_alloc(perf, ncounters); - query->oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8; - query->gpu_time_offset = 0; - query->gpu_clock_offset = query->gpu_time_offset + 1; - query->a_offset = query->gpu_clock_offset + 1; - query->b_offset = query->a_offset + 38; - query->c_offset = query->b_offset + 8; - query->perfcnt_offset = query->c_offset + 8; - query->rpstat_offset = query->perfcnt_offset + 2; return query; }
