Module: Mesa Branch: staging/23.0 Commit: 600f80c8c22f5d84a6e97164fad2772cf00f3119 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=600f80c8c22f5d84a6e97164fad2772cf00f3119
Author: Lionel Landwerlin <[email protected]> Date: Tue Mar 14 18:22:50 2023 +0200 intel/fs: don't consider fixup_nomask_control_flow SENDs predicate Those SENDs are still doing a full register write. We just inserted some predication for a workaround. Signed-off-by: Lionel Landwerlin <[email protected]> Cc: mesa-stable Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853> (cherry picked from commit 362a07db3a09d674b6f0cc7f45ab7c03d59caf88) --- .pick_status.json | 2 +- src/intel/compiler/brw_fs.cpp | 4 +++- src/intel/compiler/brw_ir.h | 6 ++++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 63bddecb14f..8dfbf1c11a4 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -175,7 +175,7 @@ "description": "intel/fs: don't consider fixup_nomask_control_flow SENDs predicate", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 03d947ff74f..a8c7db4d3ec 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -644,7 +644,8 @@ fs_visitor::limit_dispatch_width(unsigned n, const char *msg) bool fs_inst::is_partial_write() const { - if (this->predicate && this->opcode != BRW_OPCODE_SEL) + if (this->predicate && !this->predicate_trivial && + this->opcode != BRW_OPCODE_SEL) return true; if (this->dst.offset % REG_SIZE != 0) @@ -6579,6 +6580,7 @@ fs_visitor::fixup_nomask_control_flow() set_predicate(pred, inst); inst->flag_subreg = 0; + inst->predicate_trivial = true; if (save_flag) ubld.group(1, 0).at(block, inst->next).MOV(flag, tmp); diff --git a/src/intel/compiler/brw_ir.h b/src/intel/compiler/brw_ir.h index 33011f7299d..0074f74112b 100644 --- a/src/intel/compiler/brw_ir.h +++ b/src/intel/compiler/brw_ir.h @@ -178,6 +178,12 @@ struct backend_instruction { * the scratch surface offset to build * extended descriptor */ + bool predicate_trivial:1; /**< The predication mask applied to this + * instruction is guaranteed to be uniform and + * a superset of the execution mask of the + * present block, no currently enabled channels + * will be disabled by the predicate. + */ bool eot:1; /* Chooses which flag subregister (f0.0 to f1.1) is used for conditional
