Module: Mesa Branch: main Commit: dc5a9e176c2aef61ec025f116490b135cd7b9af4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc5a9e176c2aef61ec025f116490b135cd7b9af4
Author: Pierre-Eric Pelloux-Prayer <[email protected]> Date: Fri Mar 17 14:42:19 2023 +0100 amd: update amdgpu_drm.h Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986> --- include/drm-uapi/amdgpu_drm.h | 18 ++++++++++++++++++ src/amd/common/ac_gpu_info.c | 8 ++++++++ 2 files changed, 26 insertions(+) diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h index b6eb90df5d0..72041a51cc2 100644 --- a/include/drm-uapi/amdgpu_drm.h +++ b/include/drm-uapi/amdgpu_drm.h @@ -592,6 +592,7 @@ struct drm_amdgpu_gem_va { #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 +#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a struct drm_amdgpu_cs_chunk { __u32 chunk_id; @@ -708,6 +709,15 @@ struct drm_amdgpu_cs_chunk_data { }; }; +#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 + +struct drm_amdgpu_cs_chunk_cp_gfx_shadow { + __u64 shadow_va; + __u64 csa_va; + __u64 gds_va; + __u64 flags; +}; + /* * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU * @@ -1126,6 +1136,14 @@ struct drm_amdgpu_info_device { __u64 mall_size; /* AKA infinity cache */ /* high 32 bits of the rb pipes mask */ __u32 enabled_rb_pipes_mask_hi; + /* shadow area size for gfx11 */ + __u32 shadow_size; + /* shadow area base virtual alignment for gfx11 */ + __u32 shadow_alignment; + /* context save area size for gfx11 */ + __u32 csa_size; + /* context save area base virtual alignment for gfx11 */ + __u32 csa_alignment; }; struct drm_amdgpu_info_hw_ip { diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 4721ecc7a89..760b827edbb 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -196,6 +196,14 @@ struct drm_amdgpu_info_device { uint64_t mall_size; /* AKA infinity cache */ /* high 32 bits of the rb pipes mask */ uint32_t enabled_rb_pipes_mask_hi; + /* shadow area size for gfx11 */ + uint32_t shadow_size; + /* shadow area base virtual alignment for gfx11 */ + uint32_t shadow_alignment; + /* context save area size for gfx11 */ + uint32_t csa_size; + /* context save area base virtual alignment for gfx11 */ + uint32_t csa_alignment; }; struct drm_amdgpu_info_hw_ip { uint32_t hw_ip_version_major;
