Module: Mesa Branch: main Commit: bfcf03872eafedf7aba93ba758067dd121323d9a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfcf03872eafedf7aba93ba758067dd121323d9a
Author: Qiang Yu <[email protected]> Date: Wed Mar 29 15:28:28 2023 +0800 radv: implement nir_load_barycentric_optimize_amd Reviewed-by: Timur Kristóf <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199> --- src/amd/vulkan/nir/radv_nir_lower_abi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index 3b23fce6224..b5ebccf75aa 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -454,6 +454,12 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) replacement = nir_ine_imm(b, sample_coverage, 0); break; } + case nir_intrinsic_load_barycentric_optimize_amd: { + nir_ssa_def *prim_mask = ac_nir_load_arg(b, &s->args->ac, s->args->ac.prim_mask); + /* enabled when bit 31 is set */ + replacement = nir_ilt(b, prim_mask, nir_imm_int(b, 0)); + break; + } default: progress = false; break;
