Module: Mesa
Branch: main
Commit: 9fb9ae5ac69293ab60d5d1f7470d8f152ccde7f6
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fb9ae5ac69293ab60d5d1f7470d8f152ccde7f6

Author: Lionel Landwerlin <[email protected]>
Date:   Fri Apr 21 12:29:00 2023 +0300

anv: fix anv_nir_lower_ubo_loads pass

In order to use load_global_const_block_intel we need to ensure the
64bit address in src[0] is uniform. This is not the case in the
vkd3d-proton test_bindless_cbv tests for example.

Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Emma Anholt <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>

---

 src/intel/vulkan/anv_nir_lower_ubo_loads.c | 2 +-
 src/intel/vulkan/anv_pipeline.c            | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_nir_lower_ubo_loads.c 
b/src/intel/vulkan/anv_nir_lower_ubo_loads.c
index 5a170352c80..f1609a22c30 100644
--- a/src/intel/vulkan/anv_nir_lower_ubo_loads.c
+++ b/src/intel/vulkan/anv_nir_lower_ubo_loads.c
@@ -47,7 +47,7 @@ lower_ubo_load_instr(nir_builder *b, nir_instr *instr, UNUSED 
void *_data)
    unsigned byte_size = bit_size / 8;
 
    nir_ssa_def *val;
-   if (nir_src_is_const(load->src[1])) {
+   if (!nir_src_is_divergent(load->src[0]) && nir_src_is_const(load->src[1])) {
       uint32_t offset = nir_src_as_uint(load->src[1]);
 
       /* Things should be component-aligned. */
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index a8f5a2df4e6..bea64f539d6 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -954,8 +954,16 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
    NIR_PASS(_, nir, nir_copy_prop);
    NIR_PASS(_, nir, nir_opt_constant_folding);
 
+   /* Required for nir_divergence_analysis() which is needed for
+    * anv_nir_lower_ubo_loads.
+    */
+   NIR_PASS(_, nir, nir_convert_to_lcssa, true, true);
+   nir_divergence_analysis(nir);
+
    NIR_PASS(_, nir, anv_nir_lower_ubo_loads);
 
+   NIR_PASS(_, nir, nir_opt_remove_phis);
+
    enum nir_lower_non_uniform_access_type lower_non_uniform_access_types =
       nir_lower_non_uniform_texture_access | 
nir_lower_non_uniform_image_access;
 

Reply via email to