Module: Mesa Branch: main Commit: a4f96446fb9ad61504818a959c6f01ec64b0741a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4f96446fb9ad61504818a959c6f01ec64b0741a
Author: Ruijing Dong <[email protected]> Date: Tue Apr 18 16:30:47 2023 -0400 radeonsi/vcn: enable swizzle mode in encoding ref frames. swizzle mode in ref frames could potentially improve encoding performance, the main reason is just because linear mapping is the worst mode for reference frames comparing to block level mapping. Reviewed-by: Boyuan Zhang <[email protected]> Signed-off-by: Ruijing Dong <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585> --- src/gallium/drivers/radeonsi/radeon_vcn_enc.h | 2 ++ src/gallium/drivers/radeonsi/radeon_vcn_enc_2_0.c | 11 ++++++++++- src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c | 11 ++++++++++- src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c | 11 ++++++++++- 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.h b/src/gallium/drivers/radeonsi/radeon_vcn_enc.h index 5b0646d31bc..d032df574a7 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.h +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.h @@ -162,6 +162,8 @@ #define RENCODE_REC_SWIZZLE_MODE_LINEAR 0 #define RENCODE_REC_SWIZZLE_MODE_256B_S 1 +#define RENCODE_REC_SWIZZLE_MODE_256B_D 2 +#define RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP 0x10000001 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1 diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_2_0.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_2_0.c index 3d285fd0f71..202e59d1015 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_2_0.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_2_0.c @@ -461,9 +461,18 @@ static void radeon_enc_output_format(struct radeon_encoder *enc) RADEON_ENC_END(); } +static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc) +{ + /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */ + if (enc->enc_pic.bit_depth_luma_minus8 != 0) + return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP; + else + return RENCODE_REC_SWIZZLE_MODE_256B_S; +} + static void radeon_enc_ctx(struct radeon_encoder *enc) { - enc->enc_pic.ctx_buf.swizzle_mode = 0; + enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc); enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0; RADEON_ENC_BEGIN(enc->cmd.ctx); diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c index cd78079dd4e..e2f7fbd23c0 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c @@ -169,9 +169,18 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc) RADEON_ENC_END(); } +static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc) +{ + /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */ + if (enc->enc_pic.bit_depth_luma_minus8 != 0) + return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP; + else + return RENCODE_REC_SWIZZLE_MODE_256B_S; +} + static void radeon_enc_ctx(struct radeon_encoder *enc) { - enc->enc_pic.ctx_buf.swizzle_mode = 0; + enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc); enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0; RADEON_ENC_BEGIN(enc->cmd.ctx); diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c index 4015d0af48a..52b5b86b1e1 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c @@ -60,9 +60,18 @@ static void radeon_enc_sq_destroy(struct radeon_encoder *enc) rvcn_sq_tail(&enc->cs, &enc->sq); } +static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc) +{ + /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */ + if (enc->enc_pic.bit_depth_luma_minus8 != 0) + return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP; + else + return RENCODE_REC_SWIZZLE_MODE_256B_D; +} + static void radeon_enc_ctx(struct radeon_encoder *enc) { - enc->enc_pic.ctx_buf.swizzle_mode = 0; + enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc); enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0; enc->enc_pic.ctx_buf.colloc_buffer_offset = enc->dpb_size;
