Module: Mesa Branch: main Commit: 80f878b103c7113ab2ef80068b4c3e2aaceb3748 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=80f878b103c7113ab2ef80068b4c3e2aaceb3748
Author: Danylo Piliaiev <[email protected]> Date: Tue Feb 21 15:50:52 2023 +0100 ir3/a7xx: Add new form of stg.a/ldg.a addressing The new stg.a/ldg.a addressing form supersedes the a6xx's one. The new form is: ldg.a.f32 r4.y, g[c0.z+r4.y+2], 4 There are no shift comparing to the a6xx: ldg.a.f32 r4.y, g[r0.z+(r4.y)<<2], 4 Also on a7xx the first src is allowed to be both const and gpr. Signed-off-by: Danylo Piliaiev <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498> --- src/freedreno/ir3/ir3_parser.y | 32 +++++++----- src/freedreno/ir3/tests/disasm.c | 6 +++ src/freedreno/isa/ir3-cat6.xml | 106 +++++++++++++++++++++++++++++++++++---- 3 files changed, 123 insertions(+), 21 deletions(-) diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y index 5da14bc13a9..199aca1aa8e 100644 --- a/src/freedreno/ir3/ir3_parser.y +++ b/src/freedreno/ir3/ir3_parser.y @@ -1120,20 +1120,28 @@ cat6_dst_offset: offset { instr->cat6.dst_offset = $1; } cat6_immed: integer { instr->cat6.iim_val = $1; } -cat6_stg_ldg_a6xx_offset: - '+' '(' src offset ')' '<' '<' integer { - assert($8 == 2); - new_src(0, IR3_REG_IMMED)->uim_val = 0; +cat6_a6xx_global_address_pt3: + '<' '<' integer offset '<' '<' integer { + assert($7 == 2); + new_src(0, IR3_REG_IMMED)->uim_val = $3 - 2; new_src(0, IR3_REG_IMMED)->uim_val = $4; - } -| '+' src '<' '<' integer offset '<' '<' integer { - assert($9 == 2); - new_src(0, IR3_REG_IMMED)->uim_val = $5 - 2; - new_src(0, IR3_REG_IMMED)->uim_val = $6; - } + } +| '+' cat6_reg_or_immed + +cat6_a6xx_global_address_pt2: + '(' src offset ')' '<' '<' integer { + assert($7 == 2); + new_src(0, IR3_REG_IMMED)->uim_val = 0; + new_src(0, IR3_REG_IMMED)->uim_val = $3; + } + +| src cat6_a6xx_global_address_pt3 + +cat6_a6xx_global_address: + src_reg_or_const '+' cat6_a6xx_global_address_pt2 cat6_load: T_OP_LDG { new_instr(OPC_LDG); } cat6_type dst_reg ',' 'g' '[' src cat6_offset ']' ',' immediate -| T_OP_LDG_A { new_instr(OPC_LDG_A); } cat6_type dst_reg ',' 'g' '[' src cat6_stg_ldg_a6xx_offset ']' ',' immediate +| T_OP_LDG_A { new_instr(OPC_LDG_A); } cat6_type dst_reg ',' 'g' '[' cat6_a6xx_global_address ']' ',' immediate | T_OP_LDP { new_instr(OPC_LDP); } cat6_type dst_reg ',' 'p' '[' src cat6_offset ']' ',' immediate | T_OP_LDL { new_instr(OPC_LDL); } cat6_type dst_reg ',' 'l' '[' src cat6_offset ']' ',' immediate | T_OP_LDLW { new_instr(OPC_LDLW); } cat6_type dst_reg ',' 'l' '[' src cat6_offset ']' ',' immediate @@ -1142,7 +1150,7 @@ cat6_load: T_OP_LDG { new_instr(OPC_LDG); } cat6_type dst_reg ',' 'g } ',' immediate cat6_store: T_OP_STG { new_instr(OPC_STG); dummy_dst(); } cat6_type 'g' '[' src cat6_imm_offset ']' ',' src ',' immediate -| T_OP_STG_A { new_instr(OPC_STG_A); dummy_dst(); } cat6_type 'g' '[' src cat6_stg_ldg_a6xx_offset ']' ',' src ',' immediate +| T_OP_STG_A { new_instr(OPC_STG_A); dummy_dst(); } cat6_type 'g' '[' cat6_a6xx_global_address ']' ',' src ',' immediate | T_OP_STP { new_instr(OPC_STP); dummy_dst(); } cat6_type 'p' '[' src cat6_dst_offset ']' ',' src ',' immediate | T_OP_STL { new_instr(OPC_STL); dummy_dst(); } cat6_type 'l' '[' src cat6_dst_offset ']' ',' src ',' immediate | T_OP_STLW { new_instr(OPC_STLW); dummy_dst(); } cat6_type 'l' '[' src cat6_dst_offset ']' ',' src ',' immediate diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c index 3d02aa1657a..76fad0d0042 100644 --- a/src/freedreno/ir3/tests/disasm.c +++ b/src/freedreno/ir3/tests/disasm.c @@ -211,6 +211,9 @@ static const struct test { INSTR_6XX(c0d61104_01800228, "stg.a.u32 g[r2.x+(r1.x+1)<<2], r5.x, 1"), INSTR_6XX(c0d61104_01802628, "stg.a.u32 g[r2.x+r1.x<<4+3<<2], r5.x, 1"), + INSTR_7XX(c0d20505_07bfc006, "stg.a.f32 g[r0.z+r1.y+255], r0.w, 7"), + INSTR_7XX(c0d20507_04812006, "stg.a.f32 g[c0.z+r1.w+4], r0.w, 4"), + INSTR_6XX(c0020011_04c08023, "ldg.a.f32 r4.y, g[r0.z+(r4.y)<<2], 4"), /* ldg.a.f32 r4.y, g[r0.z+(r4.y<<2)], 4 */ INSTR_6XX(c0060006_01c18017, "ldg.a.u32 r1.z, g[r1.z+(r2.w)<<2], 1"), /* ldg.a.u32 r1.z, g[r1.z+(r2.w<<2)], 1 */ INSTR_6XX(c0060006_0181800f, "ldg.u32 r1.z, g[r1.z+7], 1"), @@ -230,6 +233,9 @@ static const struct test { INSTR_6XX(c0060006_0181800f, "ldg.u32 r1.z, g[r1.z+7], 1"), INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"), + INSTR_7XX(c0020411_04c08023, "ldg.a.f32 r4.y, g[r0.z+r4.y+2], 4"), + INSTR_7XX(c0004006_01c1a017, "ldg.a.f16 hr1.z, g[c1.z+r2.w+32], 1"), + /* dEQP-GLES3.functional.ubo.random.basic_arrays.0 */ INSTR_6XX(c7020020_01800000, "stc.f32 c[32], r0.x, 1"), /* stc c[32], r0.x, 1 */ /* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */ diff --git a/src/freedreno/isa/ir3-cat6.xml b/src/freedreno/isa/ir3-cat6.xml index 9d6048b1040..ccee2e29788 100644 --- a/src/freedreno/isa/ir3-cat6.xml +++ b/src/freedreno/isa/ir3-cat6.xml @@ -54,13 +54,18 @@ SOFTWARE. <bitset name="#instruction-cat6-ldg" extends="#instruction-cat6-a3xx"> <pattern pos="0" >1</pattern> - <field low="14" high="21" name="SRC1" type="#reg-gpr"/> + <field low="14" high="21" name="SRC1" type="#cat6-src-const-or-gpr"> + <param name="SRC1_CONST" as="SRC_CONST"/> + </field> <pattern pos="23" >1</pattern> - <field low="24" high="31" name="SIZE" type="uint"/> + <field low="24" high="26" name="SIZE" type="uint"/> + <pattern low="27" high="31">00xxx</pattern> <field low="32" high="39" name="DST" type="#reg-gpr"/> - <pattern low="40" high="48">xxxxxxxxx</pattern> + <pattern pos="40">x</pattern> <pattern low="52" high="53">00</pattern> <pattern low="54" high="58">00000</pattern> <!-- OPC --> + + <derived name="SRC1_CONST" expr="#false" type="bool"/> </bitset> <bitset name="ldg" extends="#instruction-cat6-ldg"> @@ -74,6 +79,7 @@ SOFTWARE. <field low="1" high="13" name="OFF" type="offset"/> <pattern pos="22" >0</pattern> <!-- Imm offset ldg form --> + <pattern low="41" high="48">xxxxxxxx</pattern> <encode> <map name="OFF">extract_reg_iim(src->srcs[1])</map> @@ -86,7 +92,7 @@ SOFTWARE. LoaD Global </doc> - <gen min="600"/> + <gen min="600" max="699"/> <display> {SY}{JP}{NAME}.{TYPE} {TYPE_HALF}{DST}, g[{SRC1}+({SRC2}{OFF})<<{SRC2_BYTE_SHIFT}], {SIZE} @@ -104,6 +110,7 @@ SOFTWARE. <assert pos="11" >0</assert> <field low="12" high="13" name="SRC2_ADD_DWORD_SHIFT" type="uint"/> <pattern pos="22" >1</pattern> <!-- Reg offset ldg form --> + <pattern low="41" high="48">xxxxxxxx</pattern> <derived name="SRC2_BYTE_SHIFT" width="3" type="uint"> <expr>{SRC2_ADD_DWORD_SHIFT} + 2</expr> @@ -117,17 +124,45 @@ SOFTWARE. </encode> </bitset> +<bitset name="ldg.a" extends="#instruction-cat6-ldg"> + <doc> + LoaD Global + </doc> + + <gen min="700"/> + + <display> + {SY}{JP}{NAME}.{TYPE} {TYPE_HALF}{DST}, g[{SRC1}+{SRC2}+{OFF}], {SIZE} + </display> + + <field low="1" high="8" name="SRC2" type="#reg-gpr"/> + <pattern low="9" high="12">xxxx</pattern> + <field pos="13" name="SRC1_CONST" type="bool"/> + <pattern pos="22" >1</pattern> <!-- Reg offset ldg form --> + <field low="41" high="48" name="OFF" type="uint"/> + + <encode> + <map name="SRC2">src->srcs[1]</map> + <map name="OFF">extract_reg_uim(src->srcs[2])</map> + <map name="SIZE">extract_reg_uim(src->srcs[3])</map> + <map name="SRC1_CONST">!!(src->srcs[0]->flags & IR3_REG_CONST)</map> + </encode> +</bitset> + <bitset name="#instruction-cat6-stg" extends="#instruction-cat6-a3xx"> <pattern pos="0" >x</pattern> <field low="1" high="8" name="SRC3" type="#reg-gpr"/> - <pattern low="14" high="21">xxxxxxxx</pattern> - <pattern low="22" high="23">1x</pattern> - <field low="24" high="31" name="SIZE" type="uint"/> + <field low="24" high="26" name="SIZE" type="uint"/> + <pattern low="27" high="31">00xxx</pattern> <field pos="40" name="DST_OFF" type="bool"/> - <field low="41" high="48" name="SRC1" type="#reg-gpr"/> + <field low="41" high="48" name="SRC1" type="#cat6-src-const-or-gpr"> + <param name="SRC1_CONST" as="SRC_CONST"/> + </field> <pattern pos="53" >x</pattern> <pattern low="54" high="58">00011</pattern> <!-- OPC --> + <derived name="SRC1_CONST" expr="#false" type="bool"/> + <encode> <map name="DST_OFF" force="true">1</map> </encode> @@ -147,6 +182,8 @@ SOFTWARE. </derived> <field low="9" high="13" name="OFF_HI" type="int"/> + <pattern low="14" high="21">xxxxxxxx</pattern> + <pattern low="22" high="23">1x</pattern> <field low="32" high="39" name="OFF_LO" type="uint"/> <pattern pos="52" >0</pattern> <!-- Imm offset stg form --> @@ -163,7 +200,7 @@ SOFTWARE. STore Global </doc> - <gen min="600"/> + <gen min="600" max="699"/> <display> {SY}{JP}{NAME}.{TYPE} g[{SRC1}+({SRC2}{OFF})<<{DST_BYTE_SHIFT}], {TYPE_HALF}{SRC3}, {SIZE} @@ -183,6 +220,8 @@ SOFTWARE. <field low="9" high="10" name="OFF" type="uoffset"/> <assert pos="11" >0</assert> <field low="12" high="13" name="SRC2_ADD_DWORD_SHIFT" type="uint"/> + <pattern low="14" high="21">xxxxxxxx</pattern> + <pattern low="22" high="23">1x</pattern> <field low="32" high="39" name="SRC2" type="#reg-gpr"/> <pattern pos="52" >1</pattern> <!-- Reg offset stg form --> @@ -195,6 +234,34 @@ SOFTWARE. </encode> </bitset> +<bitset name="stg.a" extends="#instruction-cat6-stg"> + <doc> + STore Global + </doc> + + <gen min="700"/> + + <display> + {SY}{JP}{NAME}.{TYPE} g[{SRC1}+{SRC2}+{OFF}], {TYPE_HALF}{SRC3}, {SIZE} + </display> + + <pattern low="9" high="12">xxxx</pattern> + <field pos="13" name="SRC1_CONST" type="bool"/> + <field low="14" high="21" name="OFF" type="uint"/> + <pattern pos="22" >0</pattern> <!-- Presumably SRC3_IMM --> + <pattern pos="23" >1</pattern> <!-- Presumably SIZE_IMM --> + <field low="32" high="39" name="SRC2" type="#reg-gpr"/> + <pattern pos="52" >1</pattern> + + <encode> + <map name="SRC2">src->srcs[1]</map> + <map name="OFF">extract_reg_uim(src->srcs[2])</map> + <map name="SRC3">src->srcs[3]</map> + <map name="SIZE">extract_reg_uim(src->srcs[4])</map> + <map name="SRC1_CONST">!!(src->srcs[0]->flags & IR3_REG_CONST)</map> + </encode> +</bitset> + <bitset name="#instruction-cat6-a3xx-ld" extends="#instruction-cat6-a3xx"> <pattern pos="0" >1</pattern> <field low="1" high="13" name="OFF" type="offset"/> @@ -1216,6 +1283,27 @@ SOFTWARE. </encode> </bitset> +<bitset name="#cat6-src-const-or-gpr" size="8"> + <doc> + Source value that can be either const reg or gpr + </doc> + <override> + <expr>{SRC_CONST}</expr> + <display> + c{GPR}.{SWIZ} + </display> + </override> + <display> + r{GPR}.{SWIZ} + </display> + <field name="SWIZ" low="0" high="1" type="#swiz"/> + <field name="GPR" low="2" high="7" type="uint"/> + <encode type="struct ir3_register *"> + <map name="GPR">src->num >> 2</map> + <map name="SWIZ">src->num & 0x3</map> + </encode> +</bitset> + <expr name="#cat6-direct"> {MODE} == 0 </expr>
