Module: Mesa Branch: main Commit: 11b2c54a9a44c164a55ddb3de127e8fc19a065a6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=11b2c54a9a44c164a55ddb3de127e8fc19a065a6
Author: Danylo Piliaiev <[email protected]> Date: Tue Feb 21 19:47:58 2023 +0100 ir3/a7xx: Add STSC definition STore Shared Const - loads SIZE dwords from HLSQ_SHARED_CONSTS_IMM starting from HLSQ_SHARED_CONSTS_IMM[SRC] and writing them to c[DST] Signed-off-by: Danylo Piliaiev <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498> --- src/freedreno/ir3/disasm-a3xx.c | 1 + src/freedreno/ir3/instr-a3xx.h | 1 + src/freedreno/ir3/ir3_lexer.l | 1 + src/freedreno/ir3/ir3_parser.y | 5 ++++- src/freedreno/ir3/ir3_validate.c | 1 + src/freedreno/ir3/tests/disasm.c | 6 ++++++ src/freedreno/isa/ir3-cat6.xml | 36 ++++++++++++++++++++++++++++++++++++ 7 files changed, 50 insertions(+), 1 deletion(-) diff --git a/src/freedreno/ir3/disasm-a3xx.c b/src/freedreno/ir3/disasm-a3xx.c index 18806213af9..a3b09e677fe 100644 --- a/src/freedreno/ir3/disasm-a3xx.c +++ b/src/freedreno/ir3/disasm-a3xx.c @@ -396,6 +396,7 @@ static const struct opc_info { OPC(6, OPC_GETWID, getwid), OPC(6, OPC_GETFIBERID, getfiberid), OPC(6, OPC_STC, stc), + OPC(6, OPC_STSC, stsc), OPC(6, OPC_LDC_K, ldc.k), OPC(6, OPC_SPILL_MACRO, spill.macro), diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h index 7db3c867866..4d3e0a4ff20 100644 --- a/src/freedreno/ir3/instr-a3xx.h +++ b/src/freedreno/ir3/instr-a3xx.h @@ -357,6 +357,7 @@ typedef enum { OPC_RELOAD_MACRO = _OPC(6, 80), OPC_LDC_K = _OPC(6, 81), + OPC_STSC = _OPC(6, 82), /* category 7: */ OPC_BAR = _OPC(7, 0), diff --git a/src/freedreno/ir3/ir3_lexer.l b/src/freedreno/ir3/ir3_lexer.l index 1ae46497a59..1c9d3b3cf02 100644 --- a/src/freedreno/ir3/ir3_lexer.l +++ b/src/freedreno/ir3/ir3_lexer.l @@ -378,6 +378,7 @@ static int parse_reg(const char *str) "getwid" return TOKEN(T_OP_GETWID); "getfiberid" return TOKEN(T_OP_GETFIBERID); "stc" return TOKEN(T_OP_STC); +"stsc" return TOKEN(T_OP_STSC); /* category 7: */ "bar" return TOKEN(T_OP_BAR); diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y index 199aca1aa8e..51a7be7605f 100644 --- a/src/freedreno/ir3/ir3_parser.y +++ b/src/freedreno/ir3/ir3_parser.y @@ -617,6 +617,7 @@ static void print_token(FILE *file, int type, YYSTYPE value) %token <tok> T_OP_GETWID %token <tok> T_OP_GETFIBERID %token <tok> T_OP_STC +%token <tok> T_OP_STSC /* category 7: */ %token <tok> T_OP_BAR @@ -1270,7 +1271,9 @@ stc_dst: integer { new_src(0, IR3_REG_IMMED)->iim_val = $1; } | T_A1 { new_src(0, IR3_REG_IMMED)->iim_val = 0; instr->flags |= IR3_INSTR_A1EN; } | T_A1 '+' integer { new_src(0, IR3_REG_IMMED)->iim_val = $3; instr->flags |= IR3_INSTR_A1EN; } -cat6_stc: T_OP_STC { new_instr(OPC_STC); } cat6_type 'c' '[' stc_dst ']' ',' src_reg ',' cat6_immed +cat6_stc: + T_OP_STC { new_instr(OPC_STC); } cat6_type 'c' '[' stc_dst ']' ',' src_reg ',' cat6_immed +| T_OP_STSC { new_instr(OPC_STSC); } cat6_type 'c' '[' stc_dst ']' ',' immediate ',' cat6_immed cat6_todo: T_OP_G2L { new_instr(OPC_G2L); } | T_OP_L2G { new_instr(OPC_L2G); } diff --git a/src/freedreno/ir3/ir3_validate.c b/src/freedreno/ir3/ir3_validate.c index 335b03a7d9c..1c74d711e0c 100644 --- a/src/freedreno/ir3/ir3_validate.c +++ b/src/freedreno/ir3/ir3_validate.c @@ -341,6 +341,7 @@ validate_instr(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr) validate_reg_size(ctx, instr->dsts[0], instr->cat6.type); break; case OPC_STC: + case OPC_STSC: validate_reg_size(ctx, instr->srcs[0], instr->cat6.type); validate_assert(ctx, !(instr->srcs[1]->flags & IR3_REG_HALF)); break; diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c index 76fad0d0042..f4f327c4a95 100644 --- a/src/freedreno/ir3/tests/disasm.c +++ b/src/freedreno/ir3/tests/disasm.c @@ -241,6 +241,12 @@ static const struct test { /* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */ INSTR_6XX(c7060020_03800000, "stc.u32 c[32], r0.x, 3"), /* stc c[32], r0.x, 3 */ + /* dEQP-VK.pipeline.monolithic.extended_dynamic_state.two_draws_static.stencil_state_face_both_single_gt_replace_clear_102_ref_103_depthfail */ + INSTR_7XX(c7420000_0cc00000, "stsc.f32 c[0], 0, 12"), + /* dEQP-VK.pipeline.monolithic.push_constant.graphics_pipeline.overlap_4_shaders_vert_tess_frag */ + INSTR_7XX(c7420000_08c00020, "stsc.f32 c[0], 16, 8"), + INSTR_7XX(c742006e_08c00220, "stsc.f32 c[366], 16, 8"), + /* custom */ INSTR_6XX(c7060100_03800000, "stc.u32 c[a1.x], r0.x, 3"), /* stc c[a1.x], r0.x, 3 */ INSTR_6XX(c7060120_03800000, "stc.u32 c[a1.x+32], r0.x, 3"), /* stc c[a1.x+32], r0.x, 3 */ diff --git a/src/freedreno/isa/ir3-cat6.xml b/src/freedreno/isa/ir3-cat6.xml index ccee2e29788..629172783c9 100644 --- a/src/freedreno/isa/ir3-cat6.xml +++ b/src/freedreno/isa/ir3-cat6.xml @@ -460,6 +460,42 @@ SOFTWARE. </encode> </bitset> +<bitset name="stsc" extends="#instruction-cat6-a3xx"> + <doc> + STore Shared Const - loads SIZE dwords from HLSQ_SHARED_CONSTS_IMM + starting from HLSQ_SHARED_CONSTS_IMM[SRC] and writing them to c[DST] + </doc> + <display> + {SY}{JP}{NAME}.{TYPE} c[{DST}], {SRC}, {SIZE} + </display> + <gen min="700"/> + <pattern pos="0" >x</pattern> + <field low="1" high="8" name="SRC" type="#cat6-src"> + <param name="SRC_IM"/> + </field> + <derived name="SRC_IM" expr="#true" type="bool"/> + <field low="9" high="13" name="DST_HI" type="uint"/> + <pattern low="14" high="21">xxxxxxxx</pattern> + <pattern low="22" high="23">11</pattern> + <field low="24" high="31" name="SIZE" type="uint"/> + <field low="32" high="39" name="DST_LO" type="uint"/> + <assert pos="40">0</assert> + <pattern low="41" high="48">xxxxxxxx</pattern> + <pattern low="52" high="53">xx</pattern> + <pattern low="54" high="58">11101</pattern> <!-- OPC --> + + <derived name="DST" width="13" type="uint"> + <expr>({DST_HI} << 8) | {DST_LO}</expr> + </derived> + + <encode> + <map name="DST_LO">extract_reg_uim(src->srcs[0]) & 0xff</map> + <map name="DST_HI">extract_reg_uim(src->srcs[0]) >> 8</map> + <map name="SRC">src->srcs[1]</map> + <map name="SIZE">src->cat6.iim_val</map> + </encode> +</bitset> + <bitset name="resinfo" extends="#instruction-cat6-a3xx"> <display> {SY}{JP}{NAME}.{TYPE}.{D}d {DST}, g[{SSBO}]
