Module: Mesa Branch: main Commit: 8dbd9925d5cd2d5b477393bd352ccfd8192f0ecc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8dbd9925d5cd2d5b477393bd352ccfd8192f0ecc
Author: Julia Tatz <[email protected]> Date: Wed Feb 15 00:39:57 2023 -0500 zink: Implement PIPE_CAP_OPENCL_INTEGER_FUNCTIONS and PIPE_CAP_INTEGER_MULTIPLY_32X16. Enables GL_INTEL_shader_integer_functions2 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23197> --- .../drivers/zink/nir_to_spirv/nir_to_spirv.c | 28 ++++++++++++++++++++++ src/gallium/drivers/zink/zink_device_info.py | 4 ++++ src/gallium/drivers/zink/zink_screen.c | 4 ++++ 3 files changed, 36 insertions(+) diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index 25445840764..bbabdd19ca7 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -2318,6 +2318,12 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) get_fvec_constant(ctx, bit_size, num_components, 0)); break; + case nir_op_uclz: + assert(nir_op_infos[alu->op].num_inputs == 1); + result = emit_unop(ctx, SpvOpUCountLeadingZerosINTEL, dest_type, src[0]); + spirv_builder_emit_cap(&ctx->builder, SpvCapabilityIntegerFunctions2INTEL); + spirv_builder_emit_extension(&ctx->builder, "SPV_INTEL_shader_integer_functions2"); + break; #define BUILTIN_UNOP(nir_op, spirv_op) \ case nir_op: \ assert(nir_op_infos[alu->op].num_inputs == 1); \ @@ -2449,6 +2455,28 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) BUILTIN_BINOP(nir_op_ldexp, GLSLstd450Ldexp) #undef BUILTIN_BINOP +#define INTEL_BINOP(nir_op, spirv_op) \ + case nir_op: \ + assert(nir_op_infos[alu->op].num_inputs == 2); \ + result = emit_binop(ctx, spirv_op, dest_type, src[0], src[1]); \ + spirv_builder_emit_cap(&ctx->builder, SpvCapabilityIntegerFunctions2INTEL); \ + spirv_builder_emit_extension(&ctx->builder, "SPV_INTEL_shader_integer_functions2"); \ + break; + + INTEL_BINOP(nir_op_uabs_isub, SpvOpAbsISubINTEL) + INTEL_BINOP(nir_op_uabs_usub, SpvOpAbsUSubINTEL) + INTEL_BINOP(nir_op_iadd_sat, SpvOpIAddSatINTEL) + INTEL_BINOP(nir_op_uadd_sat, SpvOpUAddSatINTEL) + INTEL_BINOP(nir_op_ihadd, SpvOpIAverageINTEL) + INTEL_BINOP(nir_op_uhadd, SpvOpUAverageINTEL) + INTEL_BINOP(nir_op_irhadd, SpvOpIAverageRoundedINTEL) + INTEL_BINOP(nir_op_urhadd, SpvOpUAverageRoundedINTEL) + INTEL_BINOP(nir_op_isub_sat, SpvOpISubSatINTEL) + INTEL_BINOP(nir_op_usub_sat, SpvOpUSubSatINTEL) + INTEL_BINOP(nir_op_imul_32x16, SpvOpIMul32x16INTEL) + INTEL_BINOP(nir_op_umul_32x16, SpvOpUMul32x16INTEL) +#undef INTEL_BINOP + case nir_op_fdot2: case nir_op_fdot3: case nir_op_fdot4: diff --git a/src/gallium/drivers/zink/zink_device_info.py b/src/gallium/drivers/zink/zink_device_info.py index 4ef8c54baa8..06062ee7e03 100644 --- a/src/gallium/drivers/zink/zink_device_info.py +++ b/src/gallium/drivers/zink/zink_device_info.py @@ -191,6 +191,10 @@ EXTENSIONS = [ alias="shader_clock", features=True, conditions=["$feats.shaderSubgroupClock"]), + Extension("VK_INTEL_shader_integer_functions2", + alias="shader_int_fns2", + features=True, + conditions=["$feats.shaderIntegerFunctions2"]), Extension("VK_EXT_sampler_filter_minmax", alias="reduction", properties=True, diff --git a/src/gallium/drivers/zink/zink_screen.c b/src/gallium/drivers/zink/zink_screen.c index c2ea90ab0df..ab7a5f2a03d 100644 --- a/src/gallium/drivers/zink/zink_screen.c +++ b/src/gallium/drivers/zink/zink_screen.c @@ -857,6 +857,10 @@ zink_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB: return screen->info.feats12.samplerFilterMinmax || screen->info.have_EXT_sampler_filter_minmax; + case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: + case PIPE_CAP_INTEGER_MULTIPLY_32X16: + return screen->info.have_INTEL_shader_integer_functions2; + case PIPE_CAP_FS_FINE_DERIVATIVE: return 1;
