Module: Mesa Branch: staging/23.1 Commit: ec6b046f8f71558d308bffb0f5effbe51b4ada0e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec6b046f8f71558d308bffb0f5effbe51b4ada0e
Author: Lionel Landwerlin <[email protected]> Date: Wed May 17 13:40:14 2023 +0300 anv: limit ANV_PIPE_RENDER_TARGET_BUFFER_WRITES to blorp operations using 3D Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rohan Garg <[email protected]> Reviewed-by: Ivan Briano <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074> (cherry-picked from commit 455a13fb7f170b0f4a55375ec3a6f006fc69f078) --- .pick_status.json | 2 +- src/intel/vulkan/anv_blorp.c | 15 ++++++++------- src/intel/vulkan/anv_private.h | 29 +++++++++++++++++++---------- src/intel/vulkan/genX_cmd_buffer.c | 16 +++++++++++----- src/intel/vulkan/genX_query.c | 13 ++++++++++--- 5 files changed, 49 insertions(+), 26 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 919ffe492dd..e760e44a5e7 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -2848,7 +2848,7 @@ "description": "anv: limit ANV_PIPE_RENDER_TARGET_BUFFER_WRITES to blorp operations using 3D", "nominated": false, "nomination_type": null, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index a8a90d5e105..1e6cfef1464 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -541,6 +541,8 @@ anv_add_buffer_write_pending_bits(struct anv_cmd_buffer *cmd_buffer, const struct intel_device_info *devinfo = cmd_buffer->device->info; cmd_buffer->state.pending_query_bits |= + (cmd_buffer->queue_family->queueFlags & VK_QUEUE_GRAPHICS_BIT) == 0 ? + ANV_QUERY_COMPUTE_WRITES_PENDING_BITS : ANV_QUERY_RENDER_TARGET_WRITES_PENDING_BITS(devinfo); } @@ -561,9 +563,9 @@ void anv_CmdCopyImageToBuffer2( &pCopyImageToBufferInfo->pRegions[r], false); } - anv_blorp_batch_finish(&batch); - anv_add_buffer_write_pending_bits(cmd_buffer, "after copy image to buffer"); + + anv_blorp_batch_finish(&batch); } static bool @@ -786,9 +788,9 @@ void anv_CmdCopyBuffer2( &pCopyBufferInfo->pRegions[r]); } - anv_blorp_batch_finish(&batch); - anv_add_buffer_write_pending_bits(cmd_buffer, "after copy buffer"); + + anv_blorp_batch_finish(&batch); } @@ -848,9 +850,9 @@ void anv_CmdUpdateBuffer( pData = (void *)pData + copy_size; } - anv_blorp_batch_finish(&batch); - anv_add_buffer_write_pending_bits(cmd_buffer, "update buffer"); + + anv_blorp_batch_finish(&batch); } void @@ -959,7 +961,6 @@ void anv_CmdFillBuffer( fillSize, data); anv_add_buffer_write_pending_bits(cmd_buffer, "after fill buffer"); - } void anv_CmdClearColorImage( diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 18bf4d537e8..bbf3003bc9a 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2097,11 +2097,13 @@ enum anv_pipe_bits { * based on PIPE_CONTROL emissions. */ enum anv_query_bits { - ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH = (1 << 0), + ANV_QUERY_WRITES_RT_FLUSH = (1 << 0), - ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH = (1 << 1), + ANV_QUERY_WRITES_TILE_FLUSH = (1 << 1), - ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL = (1 << 2), + ANV_QUERY_WRITES_CS_STALL = (1 << 2), + + ANV_QUERY_WRITES_DATA_FLUSH = (1 << 3), }; /* Things we need to flush before accessing query data using the command @@ -2116,17 +2118,24 @@ enum anv_query_bits { */ #define ANV_QUERY_RENDER_TARGET_WRITES_PENDING_BITS(devinfo) \ (((devinfo->verx10 >= 120 && \ - devinfo->verx10 < 125) ? ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH : 0) | \ - ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH | \ - ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL) + devinfo->verx10 < 125) ? ANV_QUERY_WRITES_TILE_FLUSH : 0) | \ + ANV_QUERY_WRITES_RT_FLUSH | \ + ANV_QUERY_WRITES_CS_STALL) +#define ANV_QUERY_COMPUTE_WRITES_PENDING_BITS \ + (ANV_QUERY_WRITES_DATA_FLUSH | \ + ANV_QUERY_WRITES_CS_STALL) #define ANV_PIPE_QUERY_BITS(pending_query_bits) ( \ - ((pending_query_bits & ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH) ? \ + ((pending_query_bits & ANV_QUERY_WRITES_RT_FLUSH) ? \ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0) | \ - ((pending_query_bits & ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH) ? \ + ((pending_query_bits & ANV_QUERY_WRITES_TILE_FLUSH) ? \ ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0) | \ - ((pending_query_bits & ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL) ? \ - ANV_PIPE_CS_STALL_BIT : 0)) + ((pending_query_bits & ANV_QUERY_WRITES_CS_STALL) ? \ + ANV_PIPE_CS_STALL_BIT : 0) | \ + ((pending_query_bits & ANV_QUERY_WRITES_DATA_FLUSH) ? \ + (ANV_PIPE_DATA_CACHE_FLUSH_BIT | \ + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | \ + ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT) : 0)) #define ANV_PIPE_FLUSH_BITS ( \ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \ diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 10b38e10796..5adc91a6034 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1754,16 +1754,22 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, */ if (query_bits != NULL) { if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT) - *query_bits &= ~ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH; + *query_bits &= ~ANV_QUERY_WRITES_RT_FLUSH; if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT) - *query_bits &= ~ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH; + *query_bits &= ~ANV_QUERY_WRITES_TILE_FLUSH; + + if ((bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT) && + (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT) && + (bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT)) + *query_bits &= ~ANV_QUERY_WRITES_TILE_FLUSH; /* Once RT/TILE have been flushed, we can consider the CS_STALL flush */ - if ((*query_bits & (ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH | - ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH)) == 0 && + if ((*query_bits & (ANV_QUERY_WRITES_TILE_FLUSH | + ANV_QUERY_WRITES_RT_FLUSH | + ANV_QUERY_WRITES_DATA_FLUSH)) == 0 && (bits & (ANV_PIPE_END_OF_PIPE_SYNC_BIT | ANV_PIPE_CS_STALL_BIT))) - *query_bits &= ~ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL; + *query_bits &= ~ANV_QUERY_WRITES_CS_STALL; } bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS | diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 8c3f94ecbf0..532d87df479 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -1514,15 +1514,22 @@ void genX(CmdCopyQueryPoolResults)( * command streamer. */ if (cmd_buffer->state.pending_query_bits & - ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH) + ANV_QUERY_WRITES_RT_FLUSH) needed_flushes |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT; if (cmd_buffer->state.pending_query_bits & - ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH) + ANV_QUERY_WRITES_TILE_FLUSH) needed_flushes |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; if (cmd_buffer->state.pending_query_bits & - ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL) + ANV_QUERY_WRITES_DATA_FLUSH) { + needed_flushes |= (ANV_PIPE_DATA_CACHE_FLUSH_BIT | + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | + ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT); + } + + if (cmd_buffer->state.pending_query_bits & + ANV_QUERY_WRITES_CS_STALL) needed_flushes |= ANV_PIPE_CS_STALL_BIT; /* Occlusion & timestamp queries are written using a PIPE_CONTROL and
