Module: Mesa Branch: main Commit: b66b122e0376bfbc81e167141e46f92384869dcc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b66b122e0376bfbc81e167141e46f92384869dcc
Author: Alyssa Rosenzweig <[email protected]> Date: Thu Jun 29 18:17:08 2023 -0400 pan/mdg: Fix IR from scheduling conditions If we start with unscheduled IR: 0 = comparison csel 1, 2, 0 the old code will schedule this as r31.w = comparison csel 1, 2, 0 leaving 0 as a dangling source, which can confuse the rest of the compiler. Instead rewrite this to r31.w = comparison csel 1, 2, r31.w Note the swizzle as already taken care of (i.e. turned to .x for scalar conditions) by the time we get to scheduling so we can force to .w. This keeps register allocation from doing stupid things. total instructions in shared programs: 1518138 -> 1518017 (<.01%) instructions in affected programs: 37714 -> 37593 (-0.32%) helped: 48 HURT: 42 Instructions are helped. total bundles in shared programs: 646877 -> 646756 (-0.02%) bundles in affected programs: 17024 -> 16903 (-0.71%) helped: 48 HURT: 42 Bundles are helped. total registers in shared programs: 90624 -> 90596 (-0.03%) registers in affected programs: 361 -> 333 (-7.76%) helped: 31 HURT: 5 Registers are helped. total threads in shared programs: 55561 -> 55566 (<.01%) threads in affected programs: 5 -> 10 (100.00%) helped: 4 HURT: 0 Threads are helped. total spills in shared programs: 1386 -> 1383 (-0.22%) spills in affected programs: 19 -> 16 (-15.79%) helped: 3 HURT: 0 total fills in shared programs: 5159 -> 5077 (-1.59%) fills in affected programs: 1305 -> 1223 (-6.28%) helped: 20 HURT: 0 Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Italo Nicola <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23769> --- src/panfrost/midgard/midgard_schedule.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index 7d0ebd99392..8dd258fa222 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -1013,6 +1013,7 @@ mir_schedule_condition(compiler_context *ctx, predicate->exclude = cond->dest; cond->dest = SSA_FIXED_REGISTER(31); + last->src[condition_index] = cond->dest; if (!vector) { cond->mask = (1 << COMPONENT_W); @@ -1024,6 +1025,8 @@ mir_schedule_condition(compiler_context *ctx, for (unsigned q = 0; q < 4; ++q) cond->swizzle[s][q + COMPONENT_W] = cond->swizzle[s][q]; } + + last->swizzle[condition_index][0] = COMPONENT_W; } /* Schedule the unit: csel is always in the latter pipeline, so a csel
