Module: Mesa Branch: main Commit: 66a6f48747266f9adb4c36ea3e846dae3e0647b7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66a6f48747266f9adb4c36ea3e846dae3e0647b7
Author: Sagar Ghuge <[email protected]> Date: Thu Jul 6 09:29:31 2023 -0700 anv: Drop depth cache flush requirement after depth clear/resolve >From Bspec 46959, a programming note applicable to Gfx12+: "Since HZ_OP has to be sent twice (first time set the clear/resolve state and 2nd time to clear the state), and HW internally flushes the depth cache on HZ_OP, there is no need to explicitly send a Depth Cache flush after Clear or Resolve." Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24027> --- src/intel/vulkan/anv_blorp.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index e079617375e..952daea937e 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1562,11 +1562,20 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * Even though the PRM provides a bunch of conditions under which this is * supposedly unnecessary, we choose to perform the flush unconditionally * just to be safe. + * + * From Bspec 46959, a programming note applicable to Gfx12+: + * + * "Since HZ_OP has to be sent twice (first time set the clear/resolve state + * and 2nd time to clear the state), and HW internally flushes the depth + * cache on HZ_OP, there is no need to explicitly send a Depth Cache flush + * after Clear or Resolve." */ - anv_add_pending_pipe_bits(cmd_buffer, - ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | - ANV_PIPE_DEPTH_STALL_BIT, - "after clear hiz"); + if (cmd_buffer->device->info->verx10 < 120) { + anv_add_pending_pipe_bits(cmd_buffer, + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | + ANV_PIPE_DEPTH_STALL_BIT, + "after clear hiz"); + } } static bool
