Module: Mesa Branch: main Commit: 83716b08cf103622829d84e673584781ee8850f6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=83716b08cf103622829d84e673584781ee8850f6
Author: Rohan Garg <[email protected]> Date: Fri Jul 14 12:15:33 2023 +0200 iris: migrate WA 14013910100 to use the WA framework Fixes: eeb3f4594d5 ("intel/xehp: Implement XeHP workaround Wa_14013910100.") Signed-off-by: Rohan Garg <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24156> --- src/gallium/drivers/iris/iris_state.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 49a922d40ec..2abd5ec87b0 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -430,6 +430,7 @@ flush_before_state_base_change(struct iris_batch *batch) static void flush_after_state_base_change(struct iris_batch *batch) { + const struct intel_device_info *devinfo = batch->screen->devinfo; /* After re-setting the surface state base address, we have to do some * cache flusing so that the sampler engine will pick up the new * SURFACE_STATE objects and binding tables. From the Broadwell PRM, @@ -467,7 +468,7 @@ flush_after_state_base_change(struct iris_batch *batch) * units cache the binding table in the texture cache. However, we have * yet to be able to actually confirm this. * - * Wa_14013910100: + * Wa_16013000631: * * "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice * or program pipe control with Instruction cache invalidate post @@ -478,7 +479,7 @@ flush_after_state_base_change(struct iris_batch *batch) PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_STATE_CACHE_INVALIDATE | - (GFX_VERx10 != 125 ? 0 : + (intel_needs_workaround(devinfo, 16013000631) ? 0 : PIPE_CONTROL_INSTRUCTION_INVALIDATE)); }
