Module: Mesa Branch: main Commit: f783eb9ebdeb18f1cfac48db5d68a2da612fe5d1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f783eb9ebdeb18f1cfac48db5d68a2da612fe5d1
Author: Faith Ekstrand <[email protected]> Date: Thu May 18 16:58:01 2023 -0500 intel/vec4: Assume get_nir_dest() provides a sane write-mask It should be providing a write mask that is all the channels. Drop the one case for load_input where we stomp this for no good reason. Also, make ALU write-masking AND with the existing mask. This prepares us for the next patch where we convert to new-style registers. Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104> --- src/intel/compiler/brw_vec4_nir.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index bd629115bdc..0d7eabf1bcf 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -407,7 +407,6 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) unsigned load_offset = nir_src_as_uint(instr->src[0]); dest = get_nir_dest(instr->dest); - dest.writemask = brw_writemask_for_size(instr->num_components); src = src_reg(ATTR, nir_intrinsic_base(instr) + load_offset, glsl_type::uvec4_type); @@ -1065,7 +1064,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) nir_alu_type dst_type = (nir_alu_type) (nir_op_infos[instr->op].output_type | nir_dest_bit_size(instr->dest.dest)); dst_reg dst = get_nir_dest(instr->dest.dest, dst_type); - dst.writemask = instr->dest.write_mask; + dst.writemask &= instr->dest.write_mask; assert(!instr->dest.saturate);
