Module: Mesa Branch: main Commit: a06cb572f6f7a34e13e54b78a643aacc4cd545fe URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a06cb572f6f7a34e13e54b78a643aacc4cd545fe
Author: Chia-I Wu <[email protected]> Date: Tue Jun 27 11:00:41 2023 -0700 radv: fix separate depth/stencil layouts in resolve meta Depth and stencil can be in different layouts. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22114> --- src/amd/vulkan/meta/radv_meta_resolve.c | 5 +++-- src/amd/vulkan/meta/radv_meta_resolve_cs.c | 6 ++++-- src/amd/vulkan/meta/radv_meta_resolve_fs.c | 3 ++- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_resolve.c b/src/amd/vulkan/meta/radv_meta_resolve.c index 8d29538f907..990e615830d 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve.c +++ b/src/amd/vulkan/meta/radv_meta_resolve.c @@ -291,6 +291,7 @@ radv_pick_resolve_method_images(struct radv_device *device, struct radv_image *s else if (src_image->vk.array_layers > 1 || dst_image->vk.array_layers > 1) *method = RESOLVE_COMPUTE; } else { + assert(dst_image_layout == VK_IMAGE_LAYOUT_UNDEFINED); if (src_image->vk.array_layers > 1 || dst_image->vk.array_layers > 1 || (dst_image->planes[0].surface.flags & RADEON_SURF_NO_RENDER_TARGET)) *method = RESOLVE_COMPUTE; @@ -659,10 +660,10 @@ radv_cmd_buffer_resolve_rendering(struct radv_cmd_buffer *cmd_buffer) if (render->ds_att.resolve_iview != NULL) { struct radv_image_view *src_iview = render->ds_att.iview; struct radv_image_view *dst_iview = render->ds_att.resolve_iview; - VkImageLayout dst_layout = render->ds_att.resolve_layout; radv_pick_resolve_method_images(cmd_buffer->device, src_iview->image, src_iview->vk.format, dst_iview->image, - dst_iview->vk.base_mip_level, dst_layout, cmd_buffer, &resolve_method); + dst_iview->vk.base_mip_level, VK_IMAGE_LAYOUT_UNDEFINED, cmd_buffer, + &resolve_method); if ((src_iview->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && render->ds_att.resolve_mode != VK_RESOLVE_MODE_NONE) { if (resolve_method == RESOLVE_FRAGMENT) { diff --git a/src/amd/vulkan/meta/radv_meta_resolve_cs.c b/src/amd/vulkan/meta/radv_meta_resolve_cs.c index c7315ec387a..50081a24a70 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_cs.c @@ -716,7 +716,8 @@ radv_depth_stencil_resolve_rendering_cs(struct radv_cmd_buffer *cmd_buffer, VkIm radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL); struct radv_image_view *src_iview = render->ds_att.iview; - VkImageLayout src_layout = render->ds_att.layout; + VkImageLayout src_layout = + aspects & VK_IMAGE_ASPECT_DEPTH_BIT ? render->ds_att.layout : render->ds_att.stencil_layout; struct radv_image *src_image = src_iview->image; VkImageResolve2 region = {0}; @@ -731,7 +732,8 @@ radv_depth_stencil_resolve_rendering_cs(struct radv_cmd_buffer *cmd_buffer, VkIm radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_DESCRIPTORS); struct radv_image_view *dst_iview = render->ds_att.resolve_iview; - VkImageLayout dst_layout = render->ds_att.resolve_layout; + VkImageLayout dst_layout = + aspects & VK_IMAGE_ASPECT_DEPTH_BIT ? render->ds_att.resolve_layout : render->ds_att.stencil_resolve_layout; struct radv_image *dst_image = dst_iview->image; struct radv_image_view tsrc_iview; diff --git a/src/amd/vulkan/meta/radv_meta_resolve_fs.c b/src/amd/vulkan/meta/radv_meta_resolve_fs.c index 6ffc2843625..59f64df085a 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_fs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_fs.c @@ -888,7 +888,8 @@ radv_depth_stencil_resolve_rendering_fs(struct radv_cmd_buffer *cmd_buffer, VkIm radv_emit_resolve_barrier(cmd_buffer, &barrier); struct radv_image_view *src_iview = cmd_buffer->state.render.ds_att.iview; - VkImageLayout src_layout = cmd_buffer->state.render.ds_att.layout; + VkImageLayout src_layout = + aspects & VK_IMAGE_ASPECT_DEPTH_BIT ? render->ds_att.layout : render->ds_att.stencil_layout; struct radv_image *src_image = src_iview->image; VkImageResolve2 region = {0};
