Module: Mesa Branch: main Commit: 839d6f9fa2ffa5a584390febe8523b8739a33620 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=839d6f9fa2ffa5a584390febe8523b8739a33620
Author: Konstantin Seurer <[email protected]> Date: Tue Jul 18 14:39:27 2023 +0200 radv: Stop using the misleading round_up_u* functions The functions had the same behavior as DIV_ROUND_UP but their names do not mention a division. Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24210> --- src/amd/vulkan/meta/radv_meta_clear.c | 2 +- src/amd/vulkan/radv_cmd_buffer.c | 6 +++--- src/amd/vulkan/radv_device_generated_commands.c | 2 +- src/amd/vulkan/radv_image.c | 8 ++++---- src/amd/vulkan/radv_private.h | 12 ------------ src/amd/vulkan/radv_queue.c | 6 +++--- 6 files changed, 12 insertions(+), 24 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index fb703a07dae..30e00479d60 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -597,7 +597,7 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im { struct radv_device *device = cmd_buffer->device; struct radv_meta_state *state = &device->meta_state; - uint64_t block_count = round_up_u64(size, 1024); + uint64_t block_count = DIV_ROUND_UP(size, 1024); struct radv_meta_saved_state saved_state; struct radv_buffer dst_buffer; diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 26ee4c5bf2e..eb8db73f66d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -9492,9 +9492,9 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv remainder[1] = blocks[1] + cs_block_size[1] - align_u32_npot(blocks[1], cs_block_size[1]); remainder[2] = blocks[2] + cs_block_size[2] - align_u32_npot(blocks[2], cs_block_size[2]); - blocks[0] = round_up_u32(blocks[0], cs_block_size[0]); - blocks[1] = round_up_u32(blocks[1], cs_block_size[1]); - blocks[2] = round_up_u32(blocks[2], cs_block_size[2]); + blocks[0] = DIV_ROUND_UP(blocks[0], cs_block_size[0]); + blocks[1] = DIV_ROUND_UP(blocks[1], cs_block_size[1]); + blocks[2] = DIV_ROUND_UP(blocks[2], cs_block_size[2]); for (unsigned i = 0; i < 3; ++i) { assert(offsets[i] % cs_block_size[i] == 0); diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index 09eced0534c..78dd7bd4b4a 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -1242,7 +1242,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, cmd_buffer->device->meta_state.dgc_prepare.p_layout, 0, ds_cnt, ds_writes); - unsigned block_count = MAX2(1, round_up_u32(pGeneratedCommandsInfo->sequencesCount, 64)); + unsigned block_count = MAX2(1, DIV_ROUND_UP(pGeneratedCommandsInfo->sequencesCount, 64)); vk_common_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1); radv_buffer_finish(&token_buffer); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index e46c5bab1c3..d57ba225605 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -2216,8 +2216,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, unsigned img_bw = vk_format_get_blockwidth(image->planes[iview->plane_id].format); unsigned img_bh = vk_format_get_blockheight(image->planes[iview->plane_id].format); - iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw); - iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh); + iview->extent.width = DIV_ROUND_UP(iview->extent.width * view_bw, img_bw); + iview->extent.height = DIV_ROUND_UP(iview->extent.height * view_bh, img_bh); /* Comment ported from amdvlk - * If we have the following image: @@ -2257,8 +2257,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, unsigned lvl_width = radv_minify(image->vk.extent.width, range->baseMipLevel); unsigned lvl_height = radv_minify(image->vk.extent.height, range->baseMipLevel); - lvl_width = round_up_u32(lvl_width * view_bw, img_bw); - lvl_height = round_up_u32(lvl_height * view_bh, img_bh); + lvl_width = DIV_ROUND_UP(lvl_width * view_bw, img_bw); + lvl_height = DIV_ROUND_UP(lvl_height * view_bh, img_bh); iview->extent.width = CLAMP(lvl_width << range->baseMipLevel, iview->extent.width, iview->image->planes[0].surface.u.gfx9.base_mip_width); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 4e9670d0a56..a6ffc44ef87 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -185,18 +185,6 @@ radv_is_aligned(uintmax_t n, uintmax_t a) return (n & (a - 1)) == 0; } -static inline uint32_t -round_up_u32(uint32_t v, uint32_t a) -{ - return (v + a - 1) / a; -} - -static inline uint64_t -round_up_u64(uint64_t v, uint64_t a) -{ - return (v + a - 1) / a; -} - static inline uint32_t radv_minify(uint32_t n, uint32_t levels) { diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 44f209c91b1..9f9ab90299a 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -635,12 +635,12 @@ radv_emit_graphics_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, waves /= info->num_se; radeon_set_context_reg_seq(cs, R_0286E8_SPI_TMPRING_SIZE, 3); - radeon_emit(cs, S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 256))); + radeon_emit(cs, S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, 256))); radeon_emit(cs, va >> 8); /* SPI_GFX_SCRATCH_BASE_LO */ radeon_emit(cs, va >> 40); /* SPI_GFX_SCRATCH_BASE_HI */ } else { radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, - S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024))); + S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, 1024))); } } @@ -679,7 +679,7 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, radeon_set_sh_reg( cs, R_00B860_COMPUTE_TMPRING_SIZE, - S_00B860_WAVES(waves) | S_00B860_WAVESIZE(round_up_u32(size_per_wave, info->gfx_level >= GFX11 ? 256 : 1024))); + S_00B860_WAVES(waves) | S_00B860_WAVESIZE(DIV_ROUND_UP(size_per_wave, info->gfx_level >= GFX11 ? 256 : 1024))); } static void
