Module: Mesa Branch: main Commit: d04be9770b08020dccf2eea75c135a92cd60e7d2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d04be9770b08020dccf2eea75c135a92cd60e7d2
Author: Felix DeGrood <[email protected]> Date: Tue Jul 18 18:48:48 2023 +0000 intel/compiler: use shader source hash in shader dump code Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942> --- src/gallium/drivers/iris/iris_program.c | 9 +++++++++ src/intel/compiler/brw_compiler.h | 2 ++ src/intel/compiler/brw_fs_generator.cpp | 4 ++-- src/intel/compiler/brw_vec4_generator.cpp | 10 +++++----- src/intel/vulkan/anv_pipeline.c | 7 +++++++ 5 files changed, 25 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 465526479ba..6a94366e777 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -1337,6 +1337,7 @@ iris_compile_vs(struct iris_screen *screen, .mem_ctx = mem_ctx, .nir = nir, .log_data = dbg, + .source_hash = ish->source_hash, }, .key = &brw_key, .prog_data = vs_prog_data, @@ -1491,11 +1492,14 @@ iris_compile_tcs(struct iris_screen *screen, const struct iris_tcs_prog_key *const key = &shader->key.tcs; struct brw_tcs_prog_key brw_key = iris_to_brw_tcs_key(screen, key); + uint32_t source_hash; if (ish) { nir = nir_shader_clone(mem_ctx, ish->nir); + source_hash = ish->source_hash; } else { nir = brw_nir_create_passthrough_tcs(mem_ctx, compiler, &brw_key); + source_hash = *(uint32_t*)nir->info.source_sha1; } iris_setup_uniforms(devinfo, mem_ctx, nir, prog_data, 0, &system_values, @@ -1509,6 +1513,7 @@ iris_compile_tcs(struct iris_screen *screen, .mem_ctx = mem_ctx, .nir = nir, .log_data = dbg, + .source_hash = source_hash, }, .key = &brw_key, .prog_data = tcs_prog_data, @@ -1674,6 +1679,7 @@ iris_compile_tes(struct iris_screen *screen, .mem_ctx = mem_ctx, .nir = nir, .log_data = dbg, + .source_hash = ish->source_hash, }, .key = &brw_key, .prog_data = tes_prog_data, @@ -1816,6 +1822,7 @@ iris_compile_gs(struct iris_screen *screen, .mem_ctx = mem_ctx, .nir = nir, .log_data = dbg, + .source_hash = ish->source_hash, }, .key = &brw_key, .prog_data = gs_prog_data, @@ -1955,6 +1962,7 @@ iris_compile_fs(struct iris_screen *screen, .mem_ctx = mem_ctx, .nir = nir, .log_data = dbg, + .source_hash = ish->source_hash, }, .key = &brw_key, .prog_data = fs_prog_data, @@ -2234,6 +2242,7 @@ iris_compile_cs(struct iris_screen *screen, .mem_ctx = mem_ctx, .nir = nir, .log_data = dbg, + .source_hash = ish->source_hash, }, .key = &brw_key, .prog_data = cs_prog_data, diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index ecc01a68398..17ba18fca30 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -1766,6 +1766,8 @@ struct brw_compile_params { char *error_str; uint64_t debug_flag; + + uint32_t source_hash; }; /** diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index ffacbe26f82..32324e84fd8 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2388,13 +2388,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, after_size, sha1); _mesa_sha1_format(sha1buf, sha1); - fprintf(stderr, "Native code for %s (sha1 %s)\n" + fprintf(stderr, "Native code for %s (src_hash 0x%08x) (sha1 %s)\n" "SIMD%d shader: %d instructions. %d loops. %u cycles. " "%d:%d spills:fills, %u sends, " "scheduled with mode %s. " "Promoted %u constants. " "Compacted %d to %d bytes (%.0f%%)\n", - shader_name, sha1buf, + shader_name, params->source_hash, sha1buf, dispatch_width, before_size / 16, loop_count, perf.latency, shader_stats.spill_count, diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index 5e0a1bd4127..80fae117a90 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1513,7 +1513,7 @@ generate_zero_oob_push_regs(struct brw_codegen *p, static void generate_code(struct brw_codegen *p, const struct brw_compiler *compiler, - void *log_data, + const struct brw_compile_params *params, const nir_shader *nir, struct brw_vue_prog_data *prog_data, const struct cfg_t *cfg, @@ -2238,10 +2238,10 @@ generate_code(struct brw_codegen *p, _mesa_sha1_compute(p->store, p->next_insn_offset, sha1); _mesa_sha1_format(sha1buf, sha1); - fprintf(stderr, "Native code for %s %s shader %s (sha1 %s):\n", + fprintf(stderr, "Native code for %s %s shader %s (src_hash 0x%08x) (sha1 %s):\n", nir->info.label ? nir->info.label : "unnamed", _mesa_shader_stage_to_string(nir->info.stage), nir->info.name, - sha1buf); + params->source_hash, sha1buf); fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d " "spills:fills, %u sends. Compacted %d to %d bytes (%.0f%%)\n", @@ -2260,7 +2260,7 @@ generate_code(struct brw_codegen *p, ralloc_free(disasm_info); assert(validated); - brw_shader_debug_log(compiler, log_data, + brw_shader_debug_log(compiler, params->log_data, "%s vec4 shader: %d inst, %d loops, %u cycles, " "%d:%d spills:fills, %u sends, " "compacted %d to %d bytes.\n", @@ -2292,7 +2292,7 @@ brw_vec4_generate_assembly(const struct brw_compiler *compiler, brw_init_codegen(&compiler->isa, p, params->mem_ctx); brw_set_default_access_mode(p, BRW_ALIGN_16); - generate_code(p, compiler, params->log_data, + generate_code(p, compiler, params, nir, prog_data, cfg, perf, params->stats, debug_enabled); diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index a0b8944631c..8bb767441d6 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1140,6 +1140,7 @@ anv_pipeline_compile_vs(const struct brw_compiler *compiler, .stats = vs_stage->stats, .log_data = pipeline->base.device, .mem_ctx = mem_ctx, + .source_hash = vs_stage->source_hash, }, .key = &vs_stage->key.vs, .prog_data = &vs_stage->prog_data.vs, @@ -1231,6 +1232,7 @@ anv_pipeline_compile_tcs(const struct brw_compiler *compiler, .stats = tcs_stage->stats, .log_data = device, .mem_ctx = mem_ctx, + .source_hash = tcs_stage->source_hash, }, .key = &tcs_stage->key.tcs, .prog_data = &tcs_stage->prog_data.tcs, @@ -1268,6 +1270,7 @@ anv_pipeline_compile_tes(const struct brw_compiler *compiler, .stats = tes_stage->stats, .log_data = device, .mem_ctx = mem_ctx, + .source_hash = tes_stage->source_hash, }, .key = &tes_stage->key.tes, .prog_data = &tes_stage->prog_data.tes, @@ -1306,6 +1309,7 @@ anv_pipeline_compile_gs(const struct brw_compiler *compiler, .stats = gs_stage->stats, .log_data = device, .mem_ctx = mem_ctx, + .source_hash = gs_stage->source_hash, }, .key = &gs_stage->key.gs, .prog_data = &gs_stage->prog_data.gs, @@ -1338,6 +1342,7 @@ anv_pipeline_compile_task(const struct brw_compiler *compiler, .stats = task_stage->stats, .log_data = device, .mem_ctx = mem_ctx, + .source_hash = task_stage->source_hash, }, .key = &task_stage->key.task, .prog_data = &task_stage->prog_data.task, @@ -1371,6 +1376,7 @@ anv_pipeline_compile_mesh(const struct brw_compiler *compiler, .stats = mesh_stage->stats, .log_data = device, .mem_ctx = mem_ctx, + .source_hash = mesh_stage->source_hash, }, .key = &mesh_stage->key.mesh, .prog_data = &mesh_stage->prog_data.mesh, @@ -1487,6 +1493,7 @@ anv_pipeline_compile_fs(const struct brw_compiler *compiler, .stats = fs_stage->stats, .log_data = device, .mem_ctx = mem_ctx, + .source_hash = fs_stage->source_hash, }, .key = &fs_stage->key.wm, .prog_data = &fs_stage->prog_data.wm,
