Module: Mesa Branch: main Commit: c631635f435591cfd079c2b2426a0ffabfeb9580 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c631635f435591cfd079c2b2426a0ffabfeb9580
Author: M Henning <[email protected]> Date: Sun Jul 16 21:26:48 2023 -0400 nouveau: Drop tgsi support from nv50_ir_prog_info Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175> --- src/gallium/drivers/nouveau/nouveau_compiler.c | 4 ++-- src/gallium/drivers/nouveau/nv50/nv50_program.c | 6 ++---- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 6 ++---- src/nouveau/codegen/nv50_ir.cpp | 9 +-------- src/nouveau/codegen/nv50_ir_driver.h | 4 ++-- src/nouveau/codegen/nv50_ir_from_nir.cpp | 2 +- src/nouveau/codegen/nv50_ir_serialize.cpp | 22 +--------------------- 7 files changed, 11 insertions(+), 42 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_compiler.c b/src/gallium/drivers/nouveau/nouveau_compiler.c index 93521560f96..dce5c27bf84 100644 --- a/src/gallium/drivers/nouveau/nouveau_compiler.c +++ b/src/gallium/drivers/nouveau/nouveau_compiler.c @@ -110,8 +110,8 @@ nouveau_codegen(int chipset, int type, struct tgsi_token tokens[], info.type = type; info.target = chipset; - info.bin.sourceRep = PIPE_SHADER_IR_TGSI; - info.bin.source = tokens; + _debug_printf("TGSI no longer supported\n", chipset); + // info.nir = ...; info.io.auxCBSlot = 15; info.io.ucpBase = NV50_CB_AUX_UCP_OFFSET; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c b/src/gallium/drivers/nouveau/nv50/nv50_program.c index bbfed6df9a9..523b2a74302 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_program.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c @@ -340,8 +340,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t chipset, info->type = prog->type; info->target = chipset; - info->bin.sourceRep = PIPE_SHADER_IR_NIR; - info->bin.source = (void *)nir_shader_clone(NULL, prog->nir); + info->bin.nir = nir_shader_clone(NULL, prog->nir); info->bin.smemSize = prog->cp.smem_size; info->io.auxCBSlot = 15; @@ -451,8 +450,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t chipset, info_out.bin.codeSize); out: - if (info->bin.sourceRep == PIPE_SHADER_IR_NIR) - ralloc_free((void *)info->bin.source); + ralloc_free(info->bin.nir); FREE(info); return !ret; } diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c index 3b6feb6c35a..20e418264cb 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c @@ -590,8 +590,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset, info->type = prog->type; info->target = chipset; - info->bin.sourceRep = PIPE_SHADER_IR_NIR; - info->bin.source = (void *)nir_shader_clone(NULL, prog->nir); + info->bin.nir = nir_shader_clone(NULL, prog->nir); #ifndef NDEBUG info->target = debug_get_num_option("NV50_PROG_CHIPSET", chipset); @@ -752,8 +751,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset, #endif out: - if (info->bin.sourceRep == PIPE_SHADER_IR_NIR) - ralloc_free((void *)info->bin.source); + ralloc_free((void *)info->bin.nir); FREE(info); return !ret; } diff --git a/src/nouveau/codegen/nv50_ir.cpp b/src/nouveau/codegen/nv50_ir.cpp index eb9d7192f45..7f0aec4b068 100644 --- a/src/nouveau/codegen/nv50_ir.cpp +++ b/src/nouveau/codegen/nv50_ir.cpp @@ -1309,14 +1309,7 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info, prog->dbgFlags = info->dbgFlags; prog->optLevel = info->optLevel; - switch (info->bin.sourceRep) { - case PIPE_SHADER_IR_NIR: - ret = prog->makeFromNIR(info, info_out) ? 0 : -2; - break; - default: - ret = -1; - break; - } + ret = prog->makeFromNIR(info, info_out) ? 0 : -2; if (ret < 0) goto out; if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE) diff --git a/src/nouveau/codegen/nv50_ir_driver.h b/src/nouveau/codegen/nv50_ir_driver.h index 585e76b9246..8a3f637b98e 100644 --- a/src/nouveau/codegen/nv50_ir_driver.h +++ b/src/nouveau/codegen/nv50_ir_driver.h @@ -27,6 +27,7 @@ #include "util/blob.h" #define NV50_CODEGEN_MAX_VARYINGS 80 +struct nir_shader; struct nir_shader_compiler_options; /* @@ -93,8 +94,7 @@ struct nv50_ir_prog_info struct { uint32_t smemSize; /* required shared memory per block */ - uint8_t sourceRep; /* PIPE_SHADER_IR_* */ - const void *source; + struct nir_shader *nir; } bin; union { diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp index be3adda8519..6c8b78365c6 100644 --- a/src/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp @@ -3291,7 +3291,7 @@ bool Program::makeFromNIR(struct nv50_ir_prog_info *info, struct nv50_ir_prog_info_out *info_out) { - nir_shader *nir = (nir_shader*)info->bin.source; + nir_shader *nir = info->bin.nir; Converter converter(this, nir, info, info_out); bool result = converter.run(); if (!result) diff --git a/src/nouveau/codegen/nv50_ir_serialize.cpp b/src/nouveau/codegen/nv50_ir_serialize.cpp index fd3b3810389..6f636c9a19f 100644 --- a/src/nouveau/codegen/nv50_ir_serialize.cpp +++ b/src/nouveau/codegen/nv50_ir_serialize.cpp @@ -3,7 +3,6 @@ #include "nv50_ir.h" #include "nv50_ir_target.h" #include "nv50_ir_driver.h" -#include "tgsi/tgsi_parse.h" #include "compiler/nir/nir_serialize.h" enum FixupApplyFunc { @@ -27,27 +26,8 @@ nv50_ir_prog_info_serialize(struct blob *blob, struct nv50_ir_prog_info *info) blob_write_uint8(blob, info->optLevel); blob_write_uint8(blob, info->dbgFlags); blob_write_uint8(blob, info->omitLineNum); - blob_write_uint8(blob, info->bin.sourceRep); - switch(info->bin.sourceRep) { - case PIPE_SHADER_IR_TGSI: { - struct tgsi_token *tokens = (struct tgsi_token *)info->bin.source; - unsigned int num_tokens = tgsi_num_tokens(tokens); - - blob_write_uint32(blob, num_tokens); - blob_write_bytes(blob, tokens, num_tokens * sizeof(struct tgsi_token)); - break; - } - case PIPE_SHADER_IR_NIR: { - struct nir_shader *nir = (struct nir_shader *)info->bin.source; - nir_serialize(blob, nir, true); - break; - } - default: - ERROR("unhandled info->bin.sourceRep switch case\n"); - assert(false); - return false; - } + nir_serialize(blob, info->bin.nir, true); if (info->type == PIPE_SHADER_COMPUTE) blob_write_bytes(blob, &info->prop.cp, sizeof(info->prop.cp));
