Module: Mesa Branch: main Commit: b135149986af4ce772040258f2a3a3977c6dafe2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b135149986af4ce772040258f2a3a3977c6dafe2
Author: Samuel Pitoiset <[email protected]> Date: Fri Aug 4 18:02:00 2023 +0200 radv: update cmdbuf scratch size info when shaders are bound This will automatically update the scratch size info for shader object. Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24502> --- src/amd/vulkan/radv_cmd_buffer.c | 33 +++++++++++++++++++++------------ src/amd/vulkan/radv_pipeline.c | 12 ------------ src/amd/vulkan/radv_pipeline_compute.c | 1 - src/amd/vulkan/radv_pipeline_graphics.c | 2 -- src/amd/vulkan/radv_private.h | 6 ------ 5 files changed, 21 insertions(+), 33 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d795c36934c..6c9bd8bc4a4 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6243,10 +6243,6 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_compu radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->base.cs.cdw); radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw); - cmd_buffer->compute_scratch_size_per_wave_needed = - MAX2(cmd_buffer->compute_scratch_size_per_wave_needed, pipeline->base.scratch_bytes_per_wave); - cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted, pipeline->base.max_waves); - if (pipeline->base.type == RADV_PIPELINE_COMPUTE) { radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]->bo); } else { @@ -6476,10 +6472,15 @@ radv_bind_task_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shad cmd_buffer->task_rings_needed = true; } +#define RADV_GRAPHICS_STAGES \ + (VK_SHADER_STAGE_ALL_GRAPHICS | VK_SHADER_STAGE_MESH_BIT_EXT | VK_SHADER_STAGE_TASK_BIT_EXT) + /* This function binds/unbinds a shader to the cmdbuffer state. */ static void radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader, gl_shader_stage stage) { + const struct radv_device *device = cmd_buffer->device; + if (!shader) { cmd_buffer->state.shaders[stage] = NULL; cmd_buffer->state.active_stages &= ~mesa_to_vk_shader_stage(stage); @@ -6519,7 +6520,14 @@ radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader, case MESA_SHADER_TASK: radv_bind_task_shader(cmd_buffer, shader); break; - case MESA_SHADER_COMPUTE: + case MESA_SHADER_COMPUTE: { + cmd_buffer->compute_scratch_size_per_wave_needed = + MAX2(cmd_buffer->compute_scratch_size_per_wave_needed, shader->config.scratch_bytes_per_wave); + + const unsigned max_stage_waves = radv_get_max_scratch_waves(device, shader); + cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted, max_stage_waves); + break; + } case MESA_SHADER_INTERSECTION: /* no-op */ break; @@ -6529,10 +6537,15 @@ radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader, cmd_buffer->state.shaders[stage] = shader; cmd_buffer->state.active_stages |= mesa_to_vk_shader_stage(stage); -} -#define RADV_GRAPHICS_STAGES \ - (VK_SHADER_STAGE_ALL_GRAPHICS | VK_SHADER_STAGE_MESH_BIT_EXT | VK_SHADER_STAGE_TASK_BIT_EXT) + if (mesa_to_vk_shader_stage(stage) & RADV_GRAPHICS_STAGES) { + cmd_buffer->scratch_size_per_wave_needed = + MAX2(cmd_buffer->scratch_size_per_wave_needed, shader->config.scratch_bytes_per_wave); + + const unsigned max_stage_waves = radv_get_max_scratch_waves(device, shader); + cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted, max_stage_waves); + } +} VKAPI_ATTR void VKAPI_CALL radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline _pipeline) @@ -6650,10 +6663,6 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline radv_bind_vs_input_state(cmd_buffer, graphics_pipeline); - cmd_buffer->scratch_size_per_wave_needed = - MAX2(cmd_buffer->scratch_size_per_wave_needed, pipeline->scratch_bytes_per_wave); - cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted, pipeline->max_waves); - radv_bind_multisample_state(cmd_buffer, &graphics_pipeline->ms); cmd_buffer->state.custom_blend_mode = graphics_pipeline->custom_blend_mode; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 89de2271f2a..a0bee22112c 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -126,18 +126,6 @@ radv_DestroyPipeline(VkDevice _device, VkPipeline _pipeline, const VkAllocationC radv_pipeline_destroy(device, pipeline, pAllocator); } -void -radv_pipeline_init_scratch(const struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader) -{ - if (!shader->config.scratch_bytes_per_wave) - return; - - pipeline->scratch_bytes_per_wave = MAX2(pipeline->scratch_bytes_per_wave, shader->config.scratch_bytes_per_wave); - - const unsigned max_stage_waves = radv_get_max_scratch_waves(device, shader); - pipeline->max_waves = MAX2(pipeline->max_waves, max_stage_waves); -} - static enum radv_buffer_robustness radv_convert_buffer_robustness(const struct radv_device *device, VkPipelineRobustnessBufferBehaviorEXT behaviour) { diff --git a/src/amd/vulkan/radv_pipeline_compute.c b/src/amd/vulkan/radv_pipeline_compute.c index 0d6350d84f8..9a1a9f17dba 100644 --- a/src/amd/vulkan/radv_pipeline_compute.c +++ b/src/amd/vulkan/radv_pipeline_compute.c @@ -116,7 +116,6 @@ radv_compute_pipeline_init(const struct radv_device *device, struct radv_compute const struct radv_pipeline_layout *layout, struct radv_shader *shader) { pipeline->base.need_indirect_descriptor_sets |= radv_shader_need_indirect_descriptor_sets(shader); - radv_pipeline_init_scratch(device, &pipeline->base, shader); pipeline->base.push_constant_size = layout->push_constant_size; pipeline->base.dynamic_offset_count = layout->dynamic_offset_count; diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 30bcebcc364..97a00d3d87d 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -4003,8 +4003,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv if (pipeline->base.shaders[i]) { pipeline->base.shader_upload_seq = MAX2(pipeline->base.shader_upload_seq, pipeline->base.shaders[i]->upload_seq); - - radv_pipeline_init_scratch(device, &pipeline->base, pipeline->base.shaders[i]); } } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 9cc958898c3..5ee2b33297d 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2237,9 +2237,6 @@ struct radv_pipeline { uint32_t user_data_0[MESA_VULKAN_SHADER_STAGES]; - unsigned max_waves; - unsigned scratch_bytes_per_wave; - /* Unique pipeline hash identifier. */ uint64_t pipeline_hash; @@ -2491,9 +2488,6 @@ VkPipelineShaderStageCreateInfo *radv_copy_shader_stage_create_info(struct radv_ bool radv_shader_need_indirect_descriptor_sets(const struct radv_shader *shader); -void radv_pipeline_init_scratch(const struct radv_device *device, struct radv_pipeline *pipeline, - struct radv_shader *shader); - bool radv_pipeline_has_ngg(const struct radv_graphics_pipeline *pipeline); void radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline,
