Module: Mesa Branch: staging/23.1 Commit: f0d49b6d5918e881c8a4aba7e259027dc51635ed URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0d49b6d5918e881c8a4aba7e259027dc51635ed
Author: Rhys Perry <[email protected]> Date: Fri Jul 28 18:09:33 2023 +0100 radv: fix 128bpp comp-to-single clears We were clearing GB to A, instead of R. This fixes some red tinting in Overwatch 2 when shadow quality is set to "Ultra". Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: 7451eb1d6112 ("radv: implement DCC fast clears with comp-to-single") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9446 (cherry picked from commit e2c7ce37192cef693c7a228b997402d480674a0a) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24748> --- src/amd/vulkan/meta/radv_meta_clear.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index a69898f385c..12ae813fffd 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -995,12 +995,12 @@ build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa) output_img->data.binding = 0; /* Load the clear color values. */ - nir_ssa_def *clear_values = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range = 8); + nir_ssa_def *clear_values = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 8), .range = 24); nir_ssa_def *data = nir_vec4(&b, nir_channel(&b, clear_values, 0), nir_channel(&b, clear_values, 1), - nir_channel(&b, clear_values, 1), - nir_channel(&b, clear_values, 1)); + nir_channel(&b, clear_values, 2), + nir_channel(&b, clear_values, 3)); /* Store the clear color values. */ nir_ssa_def *sample_id = is_msaa ? nir_imm_int(&b, 0) : nir_ssa_undef(&b, 1, 32); @@ -1072,7 +1072,7 @@ init_meta_clear_dcc_comp_to_single_state(struct radv_device *device) &(VkPushConstantRange){ VK_SHADER_STAGE_COMPUTE_BIT, 0, - 16, + 24, }, }; @@ -1402,16 +1402,18 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, unsigned dcc_height = DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height); - const unsigned constants[4] = { + const unsigned constants[6] = { image->planes[0].surface.u.gfx9.color.dcc_block_width, image->planes[0].surface.u.gfx9.color.dcc_block_height, color_values[0], + color_values[bytes_per_pixel == 16 ? 0 : 1], + color_values[bytes_per_pixel == 16 ? 0 : 1], color_values[1], }; radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.clear_dcc_comp_to_single_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, constants); + VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, constants); radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, layer_count);
