Module: Mesa Branch: main Commit: 871a38367147035c7778f8c80db55a00abe4aa27 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=871a38367147035c7778f8c80db55a00abe4aa27
Author: Samuel Pitoiset <[email protected]> Date: Fri Sep 8 11:41:45 2023 +0200 radv: adjust emitted prolog regs for merged shaders compiled separately It should also be the merged shader stage. Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933> --- src/amd/vulkan/radv_cmd_buffer.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index a027ceb6497..3b68bb49cc1 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3919,10 +3919,13 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v unsigned pgm_lo_reg = R_00B120_SPI_SHADER_PGM_LO_VS; unsigned rsrc1_reg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; - if (vs_shader->info.is_ngg || cmd_buffer->state.shaders[MESA_SHADER_GEOMETRY] == vs_shader) { + if (vs_shader->info.is_ngg || cmd_buffer->state.shaders[MESA_SHADER_GEOMETRY] == vs_shader || + (vs_shader->info.merged_shader_compiled_separately && vs_shader->info.next_stage == MESA_SHADER_GEOMETRY)) { pgm_lo_reg = chip >= GFX10 ? R_00B320_SPI_SHADER_PGM_LO_ES : R_00B210_SPI_SHADER_PGM_LO_ES; rsrc1_reg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; - } else if (cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL] == vs_shader) { + } else if (cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL] == vs_shader || + (vs_shader->info.merged_shader_compiled_separately && + vs_shader->info.next_stage == MESA_SHADER_TESS_CTRL)) { pgm_lo_reg = chip >= GFX10 ? R_00B520_SPI_SHADER_PGM_LO_LS : R_00B410_SPI_SHADER_PGM_LO_LS; rsrc1_reg = R_00B428_SPI_SHADER_PGM_RSRC1_HS; } else if (vs_shader->info.vs.as_ls) {
