Module: Mesa Branch: main Commit: db6e16a5158c5f8a45d4ecd639b6c8520e2dab6e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db6e16a5158c5f8a45d4ecd639b6c8520e2dab6e
Author: Samuel Pitoiset <[email protected]> Date: Tue Sep 12 15:46:49 2023 +0200 radv: enable the PKT3 CAM bit for some SPM register writes PAL does that. Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25211> --- src/amd/vulkan/radv_cs.h | 8 ++++++++ src/amd/vulkan/radv_private.h | 2 +- src/amd/vulkan/radv_spm.c | 16 +++++++++------- src/amd/vulkan/radv_sqtt.c | 2 +- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 8899cf34e57..0a4eff87694 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -142,6 +142,14 @@ radeon_set_uconfig_reg_seq_perfctr(enum amd_gfx_level gfx_level, enum radv_queue radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); } +static inline void +radeon_set_uconfig_reg_perfctr(enum amd_gfx_level gfx_level, enum radv_queue_family qf, struct radeon_cmdbuf *cs, + unsigned reg, unsigned value) +{ + radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, reg, 1); + radeon_emit(cs, value); +} + static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 6e9c0c8c527..4cd9623544e 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -3695,7 +3695,7 @@ void radv_perfcounter_emit_spm_stop(struct radv_device *device, struct radeon_cm /* radv_spm.c */ bool radv_spm_init(struct radv_device *device); void radv_spm_finish(struct radv_device *device); -void radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs); +void radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf); void radv_destroy_graphics_pipeline(struct radv_device *device, struct radv_graphics_pipeline *pipeline); void radv_destroy_graphics_lib_pipeline(struct radv_device *device, struct radv_graphics_lib_pipeline *pipeline); diff --git a/src/amd/vulkan/radv_spm.c b/src/amd/vulkan/radv_spm.c index fcb02fa7b91..1fdd9ff70bc 100644 --- a/src/amd/vulkan/radv_spm.c +++ b/src/amd/vulkan/radv_spm.c @@ -60,8 +60,9 @@ radv_spm_init_bo(struct radv_device *device) } static void -radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs) +radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf) { + const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; struct ac_spm *spm = &device->spm; for (uint32_t b = 0; b < spm->num_used_sq_block_sel; b++) { @@ -69,7 +70,7 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs) const struct ac_spm_counter_select *cntr_sel = &sq_block_sel->counters[0]; uint32_t reg_base = R_036700_SQ_PERFCOUNTER0_SELECT; - radeon_set_uconfig_reg_seq(cs, reg_base + b * 4, 1); + radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, reg_base + b * 4, 1); radeon_emit(cs, cntr_sel->sel0 | S_036700_SQC_BANK_MASK(0xf)); /* SQC_BANK_MASK only gfx10 */ } @@ -85,10 +86,10 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs) if (!cntr_sel->active) continue; - radeon_set_uconfig_reg_seq(cs, regs->select0[c], 1); + radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, regs->select0[c], 1); radeon_emit(cs, cntr_sel->sel0); - radeon_set_uconfig_reg_seq(cs, regs->select1[c], 1); + radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, regs->select1[c], 1); radeon_emit(cs, cntr_sel->sel1); } } @@ -100,8 +101,9 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs) } void -radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs) +radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf) { + const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; struct ac_spm *spm = &device->spm; uint64_t va = radv_buffer_get_va(spm->bo); uint64_t ring_size = spm->buffer_size; @@ -161,7 +163,7 @@ radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs) uint32_t *data = (uint32_t *)spm->muxsel_lines[s][l].muxsel; /* Select MUXSEL_ADDR to point to the next muxsel. */ - radeon_set_uconfig_reg(cs, rlc_muxsel_addr, l * AC_SPM_MUXSEL_LINE_SIZE); + radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, rlc_muxsel_addr, l * AC_SPM_MUXSEL_LINE_SIZE); /* Write the muxsel line configuration with MUXSEL_DATA. */ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + AC_SPM_MUXSEL_LINE_SIZE, 0)); @@ -174,7 +176,7 @@ radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs) } /* Select SPM counters. */ - radv_emit_spm_counters(device, cs); + radv_emit_spm_counters(device, cs, qf); } bool diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index 085ff7a0d02..14f71723978 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -683,7 +683,7 @@ radv_begin_sqtt(struct radv_queue *queue) /* Enable all shader stages by default. */ radv_perfcounter_emit_shaders(cs, ac_sqtt_get_shader_mask(&device->physical_device->rad_info)); - radv_emit_spm_setup(device, cs); + radv_emit_spm_setup(device, cs, family); } /* Start SQTT. */
