Module: Mesa Branch: main Commit: a9945216ba223d57ade453d5f855edd93dd3b200 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9945216ba223d57ade453d5f855edd93dd3b200
Author: Samuel Pitoiset <[email protected]> Date: Tue Sep 26 18:19:59 2023 +0200 radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue The VA needs to be adjusted, otherwise the hw always writes at offset 0. This fixes dEQP-VK.query_pool.statistics_query.*_cq. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25406> --- src/amd/vulkan/radv_query.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index cba50cd4f90..308ce1147ea 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1736,6 +1736,12 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo radv_update_hw_pipelinestat(cmd_buffer); + if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) { + uint32_t cs_invoc_offset = + radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT); + va += cs_invoc_offset; + } + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); radeon_emit(cs, va); @@ -1886,6 +1892,12 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, va += pipelinestat_block_size; + if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) { + uint32_t cs_invoc_offset = + radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT); + va += cs_invoc_offset; + } + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); radeon_emit(cs, va);
