Module: Mesa Branch: main Commit: 05fd418e8b93dbcee9e464b650f1c4b1eb76bc29 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=05fd418e8b93dbcee9e464b650f1c4b1eb76bc29
Author: Lionel Landwerlin <[email protected]> Date: Fri Sep 8 09:52:14 2023 +0300 intel/fs: handle ishl in surface/sampler rematerialization Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24554> --- src/intel/compiler/brw_fs_nir.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 36b328ef7ff..101212124e6 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4082,6 +4082,16 @@ fs_visitor::try_rebuild_resource(const brw::fs_builder &bld, nir_def *resource_d nir_resource_insts[def->index] = ubld1.SHR(dst, src0, src1); break; } + case nir_op_ishl: { + fs_reg dst = ubld1.vgrf(BRW_REGISTER_TYPE_UD); + ubld1.UNDEF(dst); + fs_reg src0 = nir_resource_insts[alu->src[0].src.ssa->index]->dst; + fs_reg src1 = nir_resource_insts[alu->src[1].src.ssa->index]->dst; + assert(src0.file != BAD_FILE && src1.file != BAD_FILE); + assert(src0.type == BRW_REGISTER_TYPE_UD); + nir_resource_insts[def->index] = ubld1.SHL(dst, src0, src1); + break; + } case nir_op_mov: { break; }
