Module: Mesa Branch: main Commit: 6b9583734b1f12db6ed1b44e7d8cb953f5439005 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b9583734b1f12db6ed1b44e7d8cb953f5439005
Author: Francisco Jerez <curroje...@riseup.net> Date: Fri Sep 29 00:48:40 2023 -0700 intel/l3: Set up L3FullWayAllocationEnable config if ALL partition has over 126 ways. L3 configurations with an ALL partition of 128 ways per bank or more cannot be represented with the normal L3ALLOC partitioning mechanism since the "All L3 client pool" field would overflow, instead the L3FullWayAllocationEnable bit has to be set, which causes the whole L3 to be used in a unified cache configuration. That's precisely the configuration we're currently using on recent platforms, but previously we were relying on the L3 config tables being empty and the selected L3 configuration being a NULL pointer to detect this condition. This is about change, the L3 configuration structure will be defined for gfx12.5+ platforms since they provide useful information about the cache hierarchy to the drivers. Instead of checking whether the pointer is NULL in order to apply a unified L3 cache configuration, use it when there is a single ALL partition larger than can be represented via L3ALLOC. Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493> --- src/gallium/drivers/iris/iris_state.c | 6 +++++- src/intel/vulkan/genX_init_state.c | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index f5776151920..c13ed9e9cf1 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -848,12 +848,16 @@ iris_emit_l3_config(struct iris_batch *batch, reg.ErrorDetectionBehaviorControl = true; reg.UseFullWays = true; #endif - if (GFX_VER < 12 || cfg) { + if (GFX_VER < 12 || (cfg && cfg->n[INTEL_L3P_ALL] <= 126)) { reg.URBAllocation = cfg->n[INTEL_L3P_URB]; reg.ROAllocation = cfg->n[INTEL_L3P_RO]; reg.DCAllocation = cfg->n[INTEL_L3P_DC]; reg.AllAllocation = cfg->n[INTEL_L3P_ALL]; } else { + assert(!cfg || !(cfg->n[INTEL_L3P_SLM] || cfg->n[INTEL_L3P_URB] || + cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_RO] || + cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_C] || + cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_TC])); #if GFX_VER >= 12 reg.L3FullWayAllocationEnable = true; #endif diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c index 7d032566b3d..9fc5b1697de 100644 --- a/src/intel/vulkan/genX_init_state.c +++ b/src/intel/vulkan/genX_init_state.c @@ -827,7 +827,11 @@ genX(emit_l3_config)(struct anv_batch *batch, #endif anv_batch_write_reg(batch, L3_ALLOCATION_REG, l3cr) { - if (cfg == NULL) { + if (cfg == NULL || (GFX_VER >= 12 && cfg->n[INTEL_L3P_ALL] > 126)) { + assert(!cfg || !(cfg->n[INTEL_L3P_SLM] || cfg->n[INTEL_L3P_URB] || + cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_RO] || + cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_C] || + cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_TC])); #if GFX_VER >= 12 l3cr.L3FullWayAllocationEnable = true; #else
