Module: Mesa Branch: main Commit: 3e3fd921acd77ca8fef1bec93de14b4ed06db18f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e3fd921acd77ca8fef1bec93de14b4ed06db18f
Author: Francisco Jerez <curroje...@riseup.net> Date: Sun May 28 16:30:23 2023 -0700 intel/mtl: Import L3 cache configurations. Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493> --- src/intel/common/intel_l3_config.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/intel/common/intel_l3_config.c b/src/intel/common/intel_l3_config.c index 0018d0acaf0..f56d41cd82e 100644 --- a/src/intel/common/intel_l3_config.c +++ b/src/intel/common/intel_l3_config.c @@ -189,9 +189,13 @@ get_l3_list(const struct intel_device_info *devinfo) return &icl_l3_list; case 12: - if (intel_device_info_is_dg2(devinfo)) + if (intel_device_info_is_dg2(devinfo) || + intel_device_info_is_mtl(devinfo)) { + /* XXX - Some MTL configs may need special-casing here, but + * we have no way to identify them right now. + */ return &dg2_l3_list; - else if (devinfo->platform == INTEL_PLATFORM_DG1 || devinfo->verx10 == 125) + } else if (devinfo->platform == INTEL_PLATFORM_DG1 || devinfo->verx10 == 125) return &empty_l3_list; else return &tgl_l3_list; @@ -341,9 +345,13 @@ intel_get_l3_config(const struct intel_device_info *devinfo, static unsigned get_l3_way_size(const struct intel_device_info *devinfo) { + /* Only MTL N/S/M have an 8KB way size, other MTL configs have 4KB + * ways. See BSpec 45319. + */ const unsigned way_size_per_bank = - (devinfo->ver >= 9 && devinfo->l3_banks == 1) || devinfo->ver >= 11 ? - 4 : 2; + devinfo->platform == INTEL_PLATFORM_MTL_M ? 8 : + (devinfo->ver >= 9 && devinfo->l3_banks == 1) || devinfo->ver >= 11 ? 4 : + 2; assert(devinfo->l3_banks); return way_size_per_bank * devinfo->l3_banks;
